mux.tan.qmsg

多路选择器 verilog CPLD EPM1270 源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:56:00 2006 " "Info: Processing started: Sat Feb 18 13:56:00 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] d\[6\] 11.859 ns Longest " "Info: Longest tpd from source pin \"b\[0\]\" to destination pin \"d\[6\]\" is 11.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns b\[0\] 1 PIN PIN_71 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'b\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/" "" "" { b[0] } "NODE_NAME" } "" } } { "mux.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/mux.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.739 ns) + CELL(0.740 ns) 4.611 ns d_tmp\[0\]~32 2 COMB LC_X13_Y4_N6 7 " "Info: 2: + IC(2.739 ns) + CELL(0.740 ns) = 4.611 ns; Loc. = LC_X13_Y4_N6; Fanout = 7; COMB Node = 'd_tmp\[0\]~32'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/" "" "3.479 ns" { b[0] d_tmp[0]~32 } "NODE_NAME" } "" } } { "mux.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/mux.v" 16 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.858 ns) + CELL(0.914 ns) 6.383 ns reduce_or~40 3 COMB LC_X13_Y4_N8 1 " "Info: 3: + IC(0.858 ns) + CELL(0.914 ns) = 6.383 ns; Loc. = LC_X13_Y4_N8; Fanout = 1; COMB Node = 'reduce_or~40'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/" "" "1.772 ns" { d_tmp[0]~32 reduce_or~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.154 ns) + CELL(2.322 ns) 11.859 ns d\[6\] 4 PIN PIN_108 0 " "Info: 4: + IC(3.154 ns) + CELL(2.322 ns) = 11.859 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'd\[6\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/" "" "5.476 ns" { reduce_or~40 d[6] } "NODE_NAME" } "" } } { "mux.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/mux.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.108 ns 43.07 % " "Info: Total cell delay = 5.108 ns ( 43.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.751 ns 56.93 % " "Info: Total interconnect delay = 6.751 ns ( 56.93 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux_cmp.qrpt" Compiler "mux" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/db/mux.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/多路选择器/" "" "11.859 ns" { b[0] d_tmp[0]~32 reduce_or~40 d[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.859 ns" { b[0] b[0]~combout d_tmp[0]~32 reduce_or~40 d[6] } { 0.000ns 0.000ns 2.739ns 0.858ns 3.154ns } { 0.000ns 1.132ns 0.740ns 0.914ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:56:01 2006 " "Info: Processing ended: Sat Feb 18 13:56:01 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}