📄 mux.tan.rpt
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Timing Analyzer report for mux
Sat Feb 18 13:56:01 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.859 ns ; b[0] ; d[6] ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM1270T144C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.859 ns ; b[0] ; d[6] ;
; N/A ; None ; 11.716 ns ; c[1] ; d[1] ;
; N/A ; None ; 11.619 ns ; b[0] ; d[1] ;
; N/A ; None ; 11.581 ns ; c[0] ; d[6] ;
; N/A ; None ; 11.538 ns ; c[1] ; d[2] ;
; N/A ; None ; 11.511 ns ; c[1] ; d[7] ;
; N/A ; None ; 11.465 ns ; b[0] ; d[2] ;
; N/A ; None ; 11.438 ns ; b[0] ; d[7] ;
; N/A ; None ; 11.420 ns ; b[1] ; d[1] ;
; N/A ; None ; 11.402 ns ; a ; d[1] ;
; N/A ; None ; 11.356 ns ; c[2] ; d[1] ;
; N/A ; None ; 11.341 ns ; c[0] ; d[1] ;
; N/A ; None ; 11.282 ns ; b[0] ; d[3] ;
; N/A ; None ; 11.279 ns ; a ; d[6] ;
; N/A ; None ; 11.276 ns ; b[0] ; d[4] ;
; N/A ; None ; 11.246 ns ; b[0] ; d[5] ;
; N/A ; None ; 11.242 ns ; b[1] ; d[2] ;
; N/A ; None ; 11.233 ns ; c[1] ; d[6] ;
; N/A ; None ; 11.228 ns ; c[2] ; d[6] ;
; N/A ; None ; 11.224 ns ; a ; d[2] ;
; N/A ; None ; 11.215 ns ; b[1] ; d[7] ;
; N/A ; None ; 11.197 ns ; a ; d[7] ;
; N/A ; None ; 11.187 ns ; c[0] ; d[2] ;
; N/A ; None ; 11.187 ns ; c[2] ; d[2] ;
; N/A ; None ; 11.184 ns ; b[2] ; d[1] ;
; N/A ; None ; 11.161 ns ; c[2] ; d[7] ;
; N/A ; None ; 11.160 ns ; c[0] ; d[7] ;
; N/A ; None ; 11.124 ns ; c[1] ; d[5] ;
; N/A ; None ; 11.122 ns ; c[2] ; d[5] ;
; N/A ; None ; 11.056 ns ; b[2] ; d[6] ;
; N/A ; None ; 11.015 ns ; b[2] ; d[2] ;
; N/A ; None ; 11.004 ns ; c[0] ; d[3] ;
; N/A ; None ; 10.998 ns ; c[0] ; d[4] ;
; N/A ; None ; 10.989 ns ; b[2] ; d[7] ;
; N/A ; None ; 10.975 ns ; a ; d[5] ;
; N/A ; None ; 10.974 ns ; c[3] ; d[1] ;
; N/A ; None ; 10.968 ns ; c[0] ; d[5] ;
; N/A ; None ; 10.950 ns ; b[2] ; d[5] ;
; N/A ; None ; 10.937 ns ; b[1] ; d[6] ;
; N/A ; None ; 10.846 ns ; c[3] ; d[6] ;
; N/A ; None ; 10.828 ns ; b[1] ; d[5] ;
; N/A ; None ; 10.761 ns ; c[3] ; d[7] ;
; N/A ; None ; 10.702 ns ; a ; d[3] ;
; N/A ; None ; 10.696 ns ; a ; d[4] ;
; N/A ; None ; 10.660 ns ; c[1] ; d[3] ;
; N/A ; None ; 10.655 ns ; c[2] ; d[3] ;
; N/A ; None ; 10.637 ns ; c[2] ; d[4] ;
; N/A ; None ; 10.636 ns ; b[3] ; d[1] ;
; N/A ; None ; 10.631 ns ; c[1] ; d[4] ;
; N/A ; None ; 10.580 ns ; c[3] ; d[5] ;
; N/A ; None ; 10.508 ns ; b[3] ; d[6] ;
; N/A ; None ; 10.483 ns ; b[2] ; d[3] ;
; N/A ; None ; 10.465 ns ; b[2] ; d[4] ;
; N/A ; None ; 10.423 ns ; b[3] ; d[7] ;
; N/A ; None ; 10.364 ns ; b[1] ; d[3] ;
; N/A ; None ; 10.335 ns ; b[1] ; d[4] ;
; N/A ; None ; 10.274 ns ; c[3] ; d[3] ;
; N/A ; None ; 10.259 ns ; c[3] ; d[2] ;
; N/A ; None ; 10.242 ns ; b[3] ; d[5] ;
; N/A ; None ; 10.237 ns ; c[3] ; d[4] ;
; N/A ; None ; 9.936 ns ; b[3] ; d[3] ;
; N/A ; None ; 9.921 ns ; b[3] ; d[2] ;
; N/A ; None ; 9.899 ns ; b[3] ; d[4] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 13:56:00 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mux -c mux
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "b[0]" to destination pin "d[6]" is 11.859 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'b[0]'
Info: 2: + IC(2.739 ns) + CELL(0.740 ns) = 4.611 ns; Loc. = LC_X13_Y4_N6; Fanout = 7; COMB Node = 'd_tmp[0]~32'
Info: 3: + IC(0.858 ns) + CELL(0.914 ns) = 6.383 ns; Loc. = LC_X13_Y4_N8; Fanout = 1; COMB Node = 'reduce_or~40'
Info: 4: + IC(3.154 ns) + CELL(2.322 ns) = 11.859 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'd[6]'
Info: Total cell delay = 5.108 ns ( 43.07 % )
Info: Total interconnect delay = 6.751 ns ( 56.93 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Feb 18 13:56:01 2006
Info: Elapsed time: 00:00:02
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