mlt.fit.qmsg

乘法器 verilog CPLD EPM1270 源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:51:54 2006 " "Info: Processing started: Sat Feb 18 13:51:54 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off mlt -c mlt " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mlt -c mlt" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "mlt EPM1270T144C5 " "Info: Selected device EPM1270T144C5 for design \"mlt\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144C5 " "Info: Device EPM570T144C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T144I5 " "Info: Device EPM570T144I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144I5 " "Info: Device EPM1270T144I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM1270T144C5ES " "Info: Device EPM1270T144C5ES is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.331 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 9.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[0\] 1 PIN PIN_71 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 7; PIN Node = 'a\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "" { a[0] } "NODE_NAME" } "" } } { "mlt.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/mlt.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.082 ns) + CELL(0.200 ns) 4.414 ns reduce_or~35 2 COMB LAB_X12_Y3 1 " "Info: 2: + IC(3.082 ns) + CELL(0.200 ns) = 4.414 ns; Loc. = LAB_X12_Y3; Fanout = 1; COMB Node = 'reduce_or~35'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "3.282 ns" { a[0] reduce_or~35 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.595 ns) + CELL(2.322 ns) 9.331 ns c\[1\] 3 PIN PIN_119 0 " "Info: 3: + IC(2.595 ns) + CELL(2.322 ns) = 9.331 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'c\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "4.917 ns" { reduce_or~35 c[1] } "NODE_NAME" } "" } } { "mlt.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/mlt.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.654 ns 39.16 % " "Info: Total cell delay = 3.654 ns ( 39.16 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.677 ns 60.84 % " "Info: Total interconnect delay = 5.677 ns ( 60.84 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "9.331 ns" { a[0] reduce_or~35 c[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:51:58 2006 " "Info: Processing ended: Sat Feb 18 13:51:58 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}