mlt.tan.qmsg

乘法器 verilog CPLD EPM1270 源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:52:04 2006 " "Info: Processing started: Sat Feb 18 13:52:04 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] c\[6\] 9.745 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"c\[6\]\" is 9.745 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[1\] 1 PIN PIN_69 7 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_69; Fanout = 7; PIN Node = 'a\[1\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "" { a[1] } "NODE_NAME" } "" } } { "mlt.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/mlt.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.740 ns) 4.603 ns reduce_or~40 2 COMB LC_X16_Y2_N6 1 " "Info: 2: + IC(2.731 ns) + CELL(0.740 ns) = 4.603 ns; Loc. = LC_X16_Y2_N6; Fanout = 1; COMB Node = 'reduce_or~40'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "3.471 ns" { a[1] reduce_or~40 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.820 ns) + CELL(2.322 ns) 9.745 ns c\[6\] 3 PIN PIN_108 0 " "Info: 3: + IC(2.820 ns) + CELL(2.322 ns) = 9.745 ns; Loc. = PIN_108; Fanout = 0; PIN Node = 'c\[6\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "5.142 ns" { reduce_or~40 c[6] } "NODE_NAME" } "" } } { "mlt.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/mlt.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.194 ns 43.04 % " "Info: Total cell delay = 4.194 ns ( 43.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.551 ns 56.96 % " "Info: Total interconnect delay = 5.551 ns ( 56.96 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt_cmp.qrpt" Compiler "mlt" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/db/mlt.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/" "" "9.745 ns" { a[1] reduce_or~40 c[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.745 ns" { a[1] a[1]~combout reduce_or~40 c[6] } { 0.000ns 0.000ns 2.731ns 2.820ns } { 0.000ns 1.132ns 0.740ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:52:04 2006 " "Info: Processing ended: Sat Feb 18 13:52:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}