mlt.fit.rpt

乘法器 verilog CPLD EPM1270 源代码

+-------+----------+---------------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+--------------+------------------+
; Name         ; Fan-Out          ;
+--------------+------------------+
; a[0]         ; 7                ;
; b[0]         ; 7                ;
; a[1]         ; 7                ;
; b[1]         ; 7                ;
; reduce_or~41 ; 1                ;
; reduce_or~40 ; 1                ;
; reduce_or~39 ; 1                ;
; reduce_or~38 ; 1                ;
; reduce_or~37 ; 1                ;
; reduce_or~36 ; 1                ;
; reduce_or~35 ; 1                ;
+--------------+------------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; C4s                        ; 25 / 2,870 ( < 1 % ) ;
; Direct links               ; 0 / 3,938 ( 0 % )    ;
; Global clocks              ; 0 / 4 ( 0 % )        ;
; LAB clocks                 ; 0 / 72 ( 0 % )       ;
; LUT chains                 ; 0 / 1,143 ( 0 % )    ;
; Local interconnects        ; 23 / 3,938 ( < 1 % ) ;
; R4s                        ; 8 / 2,832 ( < 1 % )  ;
+----------------------------+----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 1.75) ; Number of LABs  (Total = 4) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 1                           ;
; 2                                          ; 3                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 1.75) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 1                           ;
; 2                                           ; 3                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 1.75) ; Number of LABs  (Total = 4) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 1                           ;
; 2                                               ; 3                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 4.00) ; Number of LABs  (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 0                           ;
; 4                                           ; 4                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 13:51:54 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off mlt -c mlt
Info: Selected device EPM1270T144C5 for design "mlt"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is pin to pin delay of 9.331 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 7; PIN Node = 'a[0]'
    Info: 2: + IC(3.082 ns) + CELL(0.200 ns) = 4.414 ns; Loc. = LAB_X12_Y3; Fanout = 1; COMB Node = 'reduce_or~35'
    Info: 3: + IC(2.595 ns) + CELL(2.322 ns) = 9.331 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'c[1]'
    Info: Total cell delay = 3.654 ns ( 39.16 % )
    Info: Total interconnect delay = 5.677 ns ( 60.84 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sat Feb 18 13:51:58 2006
    Info: Elapsed time: 00:00:05