mlt.map.rpt

乘法器 verilog CPLD EPM1270 源代码

; Total combinational functions   ; 7         ;
;     -- Total 4-input functions  ; 7         ;
;     -- Total 3-input functions  ; 0         ;
;     -- Total 2-input functions  ; 0         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 0         ;
; I/O pins                        ; 20        ;
; Maximum fan-out node            ; b[1]      ;
; Maximum fan-out                 ; 7         ;
; Total fan-out                   ; 35        ;
; Average fan-out                 ; 1.30      ;
+---------------------------------+-----------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                      ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |mlt                       ; 7 (7)       ; 0            ; 0          ; 20   ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |mlt                ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:mult_rtl_0            ;
+------------------------------------------------+----------+---------------------+
; Parameter Name                                 ; Value    ; Type                ;
+------------------------------------------------+----------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 2        ; Untyped             ;
; LPM_WIDTHB                                     ; 2        ; Untyped             ;
; LPM_WIDTHP                                     ; 4        ; Untyped             ;
; LPM_WIDTHR                                     ; 4        ; Untyped             ;
; LPM_WIDTHS                                     ; 1        ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped             ;
; LPM_PIPELINE                                   ; 0        ; Untyped             ;
; LATENCY                                        ; 0        ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped             ;
; USE_EAB                                        ; OFF      ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped             ;
; DEVICE_FAMILY                                  ; MAX II   ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; Lut      ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped             ;
+------------------------------------------------+----------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance              ;
+---------------------------------------+---------------------+
; Name                                  ; Value               ;
+---------------------------------------+---------------------+
; Number of entity instances            ; 1                   ;
; Entity Instance                       ; lpm_mult:mult_rtl_0 ;
;     -- LPM_WIDTHA                     ; 2                   ;
;     -- LPM_WIDTHB                     ; 2                   ;
;     -- LPM_WIDTHP                     ; 4                   ;
;     -- LPM_REPRESENTATION             ; UNSIGNED            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                  ;
;     -- INPUT_B_IS_CONSTANT            ; NO                  ;
;     -- USE_EAB                        ; OFF                 ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                  ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                  ;
+---------------------------------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/乘法器/mlt.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Sat Feb 18 13:51:48 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mlt -c mlt
Info: Found 1 design units, including 1 entities, in source file mlt.v
    Info: Found entity 1: mlt
Info: Elaborating entity "mlt" for the top level hierarchy
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/multcore.tdf
    Info: Found entity 1: multcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "c[0]" stuck at VCC
    Warning: Pin "en[0]" stuck at GND
    Warning: Pin "en[1]" stuck at VCC
    Warning: Pin "en[2]" stuck at VCC
    Warning: Pin "en[3]" stuck at VCC
    Warning: Pin "en[4]" stuck at VCC
    Warning: Pin "en[5]" stuck at VCC
    Warning: Pin "en[6]" stuck at VCC
    Warning: Pin "en[7]" stuck at VCC
Info: Implemented 27 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
    Info: Implemented 7 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sat Feb 18 13:51:51 2006
    Info: Elapsed time: 00:00:03