encode.tan.qmsg

8位优先编码器 verilog CPLD EPM1270 源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 18 13:50:18 2006 " "Info: Processing started: Sat Feb 18 13:50:18 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[4\] c\[2\] 11.672 ns Longest " "Info: Longest tpd from source pin \"a\[4\]\" to destination pin \"c\[2\]\" is 11.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[4\] 1 PIN PIN_67 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_67; Fanout = 5; PIN Node = 'a\[4\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/" "" "" { a[4] } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.502 ns) + CELL(0.200 ns) 4.834 ns c_tmp~364 2 COMB LC_X14_Y7_N3 1 " "Info: 2: + IC(3.502 ns) + CELL(0.200 ns) = 4.834 ns; Loc. = LC_X14_Y7_N3; Fanout = 1; COMB Node = 'c_tmp~364'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/" "" "3.702 ns" { a[4] c_tmp~364 } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.339 ns c_tmp~365 3 COMB LC_X14_Y7_N4 4 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 5.339 ns; Loc. = LC_X14_Y7_N4; Fanout = 4; COMB Node = 'c_tmp~365'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/" "" "0.505 ns" { c_tmp~364 c_tmp~365 } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.511 ns) 6.665 ns reduce_or~512 4 COMB LC_X14_Y7_N9 1 " "Info: 4: + IC(0.815 ns) + CELL(0.511 ns) = 6.665 ns; Loc. = LC_X14_Y7_N9; Fanout = 1; COMB Node = 'reduce_or~512'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/" "" "1.326 ns" { c_tmp~365 reduce_or~512 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.685 ns) + CELL(2.322 ns) 11.672 ns c\[2\] 5 PIN PIN_117 0 " "Info: 5: + IC(2.685 ns) + CELL(2.322 ns) = 11.672 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/" "" "5.007 ns" { reduce_or~512 c[2] } "NODE_NAME" } "" } } { "encode.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/encode.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.365 ns 37.40 % " "Info: Total cell delay = 4.365 ns ( 37.40 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.307 ns 62.60 % " "Info: Total interconnect delay = 7.307 ns ( 62.60 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode_cmp.qrpt" Compiler "encode" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/db/encode.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/基础实验/8位优先编码器/" "" "11.672 ns" { a[4] c_tmp~364 c_tmp~365 reduce_or~512 c[2] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.672 ns" { a[4] a[4]~combout c_tmp~364 c_tmp~365 reduce_or~512 c[2] } { 0.000ns 0.000ns 3.502ns 0.305ns 0.815ns 2.685ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 2.322ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Feb 18 13:50:19 2006 " "Info: Processing ended: Sat Feb 18 13:50:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}