📄 encode.fit.rpt
字号:
; reduce_or~500 ; 1 ;
; reduce_or~518 ; 1 ;
; reduce_or~485 ; 1 ;
; reduce_or~517 ; 1 ;
; reduce_or~516 ; 1 ;
; reduce_or~515 ; 1 ;
; reduce_or~514 ; 1 ;
; reduce_or~513 ; 1 ;
; reduce_or~512 ; 1 ;
; c_tmp~366 ; 1 ;
; c_tmp~364 ; 1 ;
+---------------+-----------------+
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 20 / 2,870 ( < 1 % ) ;
; Direct links ; 1 / 3,938 ( < 1 % ) ;
; Global clocks ; 0 / 4 ( 0 % ) ;
; LAB clocks ; 0 / 72 ( 0 % ) ;
; LUT chains ; 4 / 1,143 ( < 1 % ) ;
; Local interconnects ; 26 / 3,938 ( < 1 % ) ;
; R4s ; 13 / 2,832 ( < 1 % ) ;
+----------------------------+----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 2) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+--------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 7.00) ; Number of LABs (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 2) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 8.00) ; Number of LABs (Total = 2) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sat Feb 18 13:50:08 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off encode -c encode
Info: Selected device EPM1270T144C5 for design "encode"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is pin to pin delay of 12.193 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 1; PIN Node = 'a[1]'
Info: 2: + IC(3.207 ns) + CELL(0.740 ns) = 5.079 ns; Loc. = LAB_X14_Y7; Fanout = 1; COMB Node = 'c_tmp~366'
Info: 3: + IC(0.983 ns) + CELL(0.200 ns) = 6.262 ns; Loc. = LAB_X14_Y7; Fanout = 4; COMB Node = 'c_tmp~367'
Info: 4: + IC(0.443 ns) + CELL(0.740 ns) = 7.445 ns; Loc. = LAB_X14_Y7; Fanout = 1; COMB Node = 'reduce_or~512'
Info: 5: + IC(2.426 ns) + CELL(2.322 ns) = 12.193 ns; Loc. = PIN_117; Fanout = 0; PIN Node = 'c[2]'
Info: Total cell delay = 5.134 ns ( 42.11 % )
Info: Total interconnect delay = 7.059 ns ( 57.89 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Feb 18 13:50:12 2006
Info: Elapsed time: 00:00:05
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