seg7led.tan.summary

Verilog HDL源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.217 ns
From           : reset
To             : segmain:inst1|count[14]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.663 ns
From           : lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_v4i:auto_generated|safe_q[1]
To             : 78leddata[1]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.374 ns
From           : reset
To             : lpm_counter0:inst|lpm_counter:lpm_counter_component|cntr_v4i:auto_generated|safe_q[15]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 184.09 MHz ( period = 5.432 ns )
From           : int_div:inst6|clk_div[28]
To             : int_div:inst6|clk_div[26]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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