spi_at45db041b.txt

用verilog编写的SPI程序,SPI芯片是AT45DB041B.文件内包含程序仿真时的截图.包括read和wirte.

/**********************************************************************************
	
    Device      : EP2C8F144C8

    File name   : spi.c

    Ver nr.		: 1.0

    Description : spi
                  								 
    Compiler    : quartusII 7.2
	 
	Author	    : hellen
 
	Change log	: 2008-09-01
**********************************************************************************/ 
  //Change log  :write buffer1 and read buffer1,but not to transit test.
module spi(clk,reset,mosi,miso,sclk,csb,write, read,spi_data,spo_data);

input 			clk;
input 			reset;
output 			mosi;
output 			sclk;
output 			csb;
input           miso,write, read;
input[7:0]      spi_data;
output[7:0]     spo_data;

reg csb;
reg [7:0] counter_si;
reg [7:0] counter_so;
reg [4:0] mosi_index;
reg mosi_reg;
reg[7:0] opcode;
//reg[7:0] spi_data;
//reg[8:0] buffer_address;
reg[7:0] miso_reg;
reg[7:0] spo_data;


//parameter spi_data = 01011010;
parameter buffer_address=000000000;


parameter  ClkFrequency = 40000000;  // 时钟频率－25 MHz
parameter  Baud = 10000000;          // 时钟频率－10 MHz      


// 波特率产生
parameter BaudGeneratorAccWidth = 16;
reg       [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
wire [BaudGeneratorAccWidth:0] BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
wire sclk_reg = BaudGeneratorAcc[BaudGeneratorAccWidth];
always @(posedge clk or negedge reset)
   if(~reset)
      BaudGeneratorAcc <= 0;
 else 
    BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;


/////////////////////////////////////////////////////
assign sclk = sclk_reg;
assign mosi = mosi_reg;


//generate a counter
always@ (negedge sclk_reg or negedge reset)
begin
  if(!reset)
    counter_si<= 0;
  else begin
    if(write)
      counter_si=counter_si + 1;
    else if(counter_si>=1 && counter_si< 42)
    counter_si=counter_si + 1;
    else  counter_si<= 0;
  end
end

//generate a counter
always@ (posedge sclk_reg or negedge reset)
begin
  if(!reset)
    counter_so<= 0;
  else begin
    if(write)
      counter_so=counter_si + 1;
    else if(counter_so>=1 && counter_so< 51)
    counter_so=counter_so + 1;
    else counter_so<= 0;
  end
end


//generate signal "csb"
always@ (posedge sclk_reg or negedge reset)
begin
  if(!reset)
    csb <=1;
  else if(counter_si>= 1 && counter_si <= 49)
    csb = 0;
  else
    csb = 1;
end


always@ (counter_si or csb)
begin
  if(csb == 0)
  case(counter_si)
    6'h00:begin
           if(write)
              opcode= 8'b10000100;
           else if(read)
              opcode= 8'b01010100;end      
    6'd01:mosi_reg= opcode[7];
    6'd02:mosi_reg= opcode[6];
    6'd03:mosi_reg= opcode[5];
    6'd04:mosi_reg= opcode[4];
    6'd05:mosi_reg= opcode[3];
    6'd06:mosi_reg= opcode[2];
    6'd07:mosi_reg= opcode[1];
    6'd08:mosi_reg= opcode[0];
    6'd09:mosi_reg= 1'b1;
    6'd10:mosi_reg= 1'b1;
    6'd11:mosi_reg= 1'b1;
    6'd12:mosi_reg= 1'b1;
    6'd13:mosi_reg= 1'b1;
    6'd14:mosi_reg= 1'b1;
    6'd15:mosi_reg= 1'b1;
    6'd16:mosi_reg= 1'b1;
    6'd17:mosi_reg= 1'b1;
    6'd18:mosi_reg= 1'b1;
    6'd19:mosi_reg= 1'b1;
    6'd20:mosi_reg= 1'b1;
    6'd21:mosi_reg= 1'b1;
    6'd22:mosi_reg= 1'b1;
    6'd23:mosi_reg= 1'b1;
    6'd24:mosi_reg= 1'b1;
    6'd25:mosi_reg= buffer_address[8];
    6'd26:mosi_reg= buffer_address[7];
    6'd27:mosi_reg= buffer_address[6];
    6'd28:mosi_reg= buffer_address[5];
    6'd29:mosi_reg= buffer_address[4];
    6'd30:mosi_reg= buffer_address[3];
    6'd31:mosi_reg= buffer_address[2];
    6'd32:mosi_reg= buffer_address[1];
    6'd33:mosi_reg= buffer_address[0];
    6'd34:mosi_reg= spi_data[7];
    6'd35:mosi_reg= spi_data[6];
    6'd36:mosi_reg= spi_data[5];
    6'd37:mosi_reg= spi_data[4];
    6'd38:mosi_reg= spi_data[3];
    6'd39:mosi_reg= spi_data[2];
    6'd40:mosi_reg= spi_data[1];
    6'd41:mosi_reg= spi_data[0];
    6'd42:mosi_reg= 1'b0;
    default:mosi_reg= 1'b0;
  endcase
  else
    mosi_reg= 1'b0;
end


always@ (counter_so or csb)
begin
  if(csb == 0)
  case(counter_so)
    6'd42:miso_reg[7]= miso;
    6'd43:miso_reg[6]= miso;
    6'd44:miso_reg[5]= miso;
    6'd45:miso_reg[4]= miso;
    6'd46:miso_reg[3]= miso;
    6'd47:miso_reg[2]= miso;
    6'd48:miso_reg[1]= miso;
    6'd49:miso_reg[0]= miso;
    6'd50:spo_data= mosi_reg;
    default:miso_reg= 1'bz;
  endcase
  else
    miso_reg= 1'bz;
end


endmodule