📄 prev_cmp_uart_tran.qmsg
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "135 " "Info: Allocated 135 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 24 09:08:26 2008 " "Info: Processing ended: Fri Oct 24 09:08:26 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 24 09:08:27 2008 " "Info: Processing started: Fri Oct 24 09:08:27 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart_tran -c uart_tran --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_tran -c uart_tran --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[4\] register cnt\[11\] 221.43 MHz 4.516 ns Internal " "Info: Clock \"clk\" has Internal fmax of 221.43 MHz between source register \"cnt\[4\]\" and destination register \"cnt\[11\]\" (period= 4.516 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.275 ns + Longest register register " "Info: + Longest register to register delay is 4.275 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[4\] 1 REG LC_X21_Y12_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y12_N2; Fanout = 4; REG Node = 'cnt\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[4] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.236 ns) + CELL(0.432 ns) 1.668 ns Add0~246COUT1 2 COMB LC_X21_Y11_N6 2 " "Info: 2: + IC(1.236 ns) + CELL(0.432 ns) = 1.668 ns; Loc. = LC_X21_Y11_N6; Fanout = 2; COMB Node = 'Add0~246COUT1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { cnt[4] Add0~246COUT1 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.748 ns Add0~248COUT1 3 COMB LC_X21_Y11_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.748 ns; Loc. = LC_X21_Y11_N7; Fanout = 2; COMB Node = 'Add0~248COUT1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~246COUT1 Add0~248COUT1 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.828 ns Add0~250COUT1 4 COMB LC_X21_Y11_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.828 ns; Loc. = LC_X21_Y11_N8; Fanout = 2; COMB Node = 'Add0~250COUT1'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Add0~248COUT1 Add0~250COUT1 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 2.086 ns Add0~252 5 COMB LC_X21_Y11_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.086 ns; Loc. = LC_X21_Y11_N9; Fanout = 6; COMB Node = 'Add0~252'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { Add0~250COUT1 Add0~252 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.765 ns Add0~259 6 COMB LC_X21_Y10_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.765 ns; Loc. = LC_X21_Y10_N3; Fanout = 1; COMB Node = 'Add0~259'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.679 ns" { Add0~252 Add0~259 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.309 ns) 4.275 ns cnt\[11\] 7 REG LC_X20_Y13_N2 4 " "Info: 7: + IC(1.201 ns) + CELL(0.309 ns) = 4.275 ns; Loc. = LC_X20_Y13_N2; Fanout = 4; REG Node = 'cnt\[11\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { Add0~259 cnt[11] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.838 ns ( 42.99 % ) " "Info: Total cell delay = 1.838 ns ( 42.99 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.437 ns ( 57.01 % ) " "Info: Total interconnect delay = 2.437 ns ( 57.01 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.275 ns" { cnt[4] Add0~246COUT1 Add0~248COUT1 Add0~250COUT1 Add0~252 Add0~259 cnt[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.275 ns" { cnt[4] {} Add0~246COUT1 {} Add0~248COUT1 {} Add0~250COUT1 {} Add0~252 {} Add0~259 {} cnt[11] {} } { 0.000ns 1.236ns 0.000ns 0.000ns 0.000ns 0.000ns 1.201ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.309ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.020 ns - Smallest " "Info: - Smallest clock skew is 0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns cnt\[11\] 2 REG LC_X20_Y13_N2 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X20_Y13_N2; Fanout = 4; REG Node = 'cnt\[11\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk cnt[11] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk cnt[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} cnt[11] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns cnt\[4\] 2 REG LC_X21_Y12_N2 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y12_N2; Fanout = 4; REG Node = 'cnt\[4\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk cnt[4] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} cnt[4] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk cnt[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} cnt[11] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} cnt[4] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.275 ns" { cnt[4] Add0~246COUT1 Add0~248COUT1 Add0~250COUT1 Add0~252 Add0~259 cnt[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.275 ns" { cnt[4] {} Add0~246COUT1 {} Add0~248COUT1 {} Add0~250COUT1 {} Add0~252 {} Add0~259 {} cnt[11] {} } { 0.000ns 1.236ns 0.000ns 0.000ns 0.000ns 0.000ns 1.201ns } { 0.000ns 0.432ns 0.080ns 0.080ns 0.258ns 0.679ns 0.309ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk cnt[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk {} clk~out0 {} cnt[11] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} cnt[4] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "data_reg\[2\] wr_en clk 5.894 ns register " "Info: tsu for register \"data_reg\[2\]\" (data pin = \"wr_en\", clock pin = \"clk\") is 5.894 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.799 ns + Longest pin register " "Info: + Longest pin to register delay is 8.799 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns wr_en 1 PIN PIN_158 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 10; PIN Node = 'wr_en'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_en } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.463 ns) + CELL(0.867 ns) 8.799 ns data_reg\[2\] 2 REG LC_X22_Y12_N7 1 " "Info: 2: + IC(6.463 ns) + CELL(0.867 ns) = 8.799 ns; Loc. = LC_X22_Y12_N7; Fanout = 1; REG Node = 'data_reg\[2\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.330 ns" { wr_en data_reg[2] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 26.55 % ) " "Info: Total cell delay = 2.336 ns ( 26.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.463 ns ( 73.45 % ) " "Info: Total interconnect delay = 6.463 ns ( 73.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.799 ns" { wr_en data_reg[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.799 ns" { wr_en {} wr_en~out0 {} data_reg[2] {} } { 0.000ns 0.000ns 6.463ns } { 0.000ns 1.469ns 0.867ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 53 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns data_reg\[2\] 2 REG LC_X22_Y12_N7 1 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X22_Y12_N7; Fanout = 1; REG Node = 'data_reg\[2\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk data_reg[2] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk data_reg[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} data_reg[2] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.799 ns" { wr_en data_reg[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.799 ns" { wr_en {} wr_en~out0 {} data_reg[2] {} } { 0.000ns 0.000ns 6.463ns } { 0.000ns 1.469ns 0.867ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk data_reg[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} data_reg[2] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clk_equ cnt\[10\] 10.280 ns register " "Info: tco from clock \"clk\" to destination pin \"clk_equ\" through register \"cnt\[10\]\" is 10.280 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns cnt\[10\] 2 REG LC_X20_Y10_N2 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y10_N2; Fanout = 4; REG Node = 'cnt\[10\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk cnt[10] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} cnt[10] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.114 ns + Longest register pin " "Info: + Longest register to pin delay is 7.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[10\] 1 REG LC_X20_Y10_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y10_N2; Fanout = 4; REG Node = 'cnt\[10\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[10] } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.279 ns) + CELL(0.590 ns) 1.869 ns Equal0~149 2 COMB LC_X21_Y12_N7 1 " "Info: 2: + IC(1.279 ns) + CELL(0.590 ns) = 1.869 ns; Loc. = LC_X21_Y12_N7; Fanout = 1; COMB Node = 'Equal0~149'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { cnt[10] Equal0~149 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.590 ns) 2.893 ns Equal0~151 3 COMB LC_X21_Y12_N8 8 " "Info: 3: + IC(0.434 ns) + CELL(0.590 ns) = 2.893 ns; Loc. = LC_X21_Y12_N8; Fanout = 8; COMB Node = 'Equal0~151'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.024 ns" { Equal0~149 Equal0~151 } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.113 ns) + CELL(2.108 ns) 7.114 ns clk_equ 4 PIN PIN_206 0 " "Info: 4: + IC(2.113 ns) + CELL(2.108 ns) = 7.114 ns; Loc. = PIN_206; Fanout = 0; PIN Node = 'clk_equ'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.221 ns" { Equal0~151 clk_equ } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.288 ns ( 46.22 % ) " "Info: Total cell delay = 3.288 ns ( 46.22 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.826 ns ( 53.78 % ) " "Info: Total interconnect delay = 3.826 ns ( 53.78 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.114 ns" { cnt[10] Equal0~149 Equal0~151 clk_equ } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.114 ns" { cnt[10] {} Equal0~149 {} Equal0~151 {} clk_equ {} } { 0.000ns 1.279ns 0.434ns 2.113ns } { 0.000ns 0.590ns 0.590ns 2.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk cnt[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} cnt[10] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.114 ns" { cnt[10] Equal0~149 Equal0~151 clk_equ } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.114 ns" { cnt[10] {} Equal0~149 {} Equal0~151 {} clk_equ {} } { 0.000ns 1.279ns 0.434ns 2.113ns } { 0.000ns 0.590ns 0.590ns 2.108ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "contral reset clk -0.719 ns register " "Info: th for register \"contral\" (data pin = \"reset\", clock pin = \"clk\") is -0.719 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns contral 2 REG LC_X23_Y12_N9 2 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X23_Y12_N9; Fanout = 2; REG Node = 'contral'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk contral } "NODE_NAME" } } { "uart_tran.v" "" { Text "E:/FPGA_Project/uart_tran/uart_tran.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk contral } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk {} clk~out0 {} contral {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro ⌨️ 快捷键说明
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