uart_tran.tan.rpt

UART串口的传送verilog原程序

; N/A   ; None         ; 9.785 ns   ; cnt[9]        ; clk_equ  ; clk        ;
; N/A   ; None         ; 9.384 ns   ; cnt[13]       ; clk_equ  ; clk        ;
; N/A   ; None         ; 9.109 ns   ; cnt[0]        ; clk_equ  ; clk        ;
; N/A   ; None         ; 8.889 ns   ; complete~reg0 ; complete ; clk        ;
; N/A   ; None         ; 8.789 ns   ; cnt[8]        ; clk_equ  ; clk        ;
; N/A   ; None         ; 8.637 ns   ; cnt[12]       ; clk_equ  ; clk        ;
; N/A   ; None         ; 8.508 ns   ; cnt[4]        ; clk_equ  ; clk        ;
; N/A   ; None         ; 8.187 ns   ; data_out~reg0 ; data_out ; clk        ;
+-------+--------------+------------+---------------+----------+------------+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+---------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To          ; To Clock ;
+---------------+-------------+-----------+---------+-------------+----------+
; N/A           ; None        ; -0.719 ns ; reset   ; contral     ; clk      ;
; N/A           ; None        ; -4.533 ns ; data[0] ; data_reg[1] ; clk      ;
; N/A           ; None        ; -4.537 ns ; data[4] ; data_reg[5] ; clk      ;
; N/A           ; None        ; -4.539 ns ; data[7] ; data_reg[8] ; clk      ;
; N/A           ; None        ; -4.553 ns ; data[2] ; data_reg[3] ; clk      ;
; N/A           ; None        ; -4.755 ns ; data[6] ; data_reg[7] ; clk      ;
; N/A           ; None        ; -4.764 ns ; data[1] ; data_reg[2] ; clk      ;
; N/A           ; None        ; -4.926 ns ; data[3] ; data_reg[4] ; clk      ;
; N/A           ; None        ; -4.938 ns ; data[5] ; data_reg[6] ; clk      ;
; N/A           ; None        ; -5.042 ns ; wr_en   ; contral     ; clk      ;
; N/A           ; None        ; -5.774 ns ; wr_en   ; data_reg[9] ; clk      ;
; N/A           ; None        ; -5.774 ns ; wr_en   ; data_reg[7] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[2] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[3] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[8] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[1] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[4] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[5] ; clk      ;
; N/A           ; None        ; -5.842 ns ; wr_en   ; data_reg[6] ; clk      ;
+---------------+-------------+-----------+---------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Oct 24 09:08:27 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_tran -c uart_tran --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 221.43 MHz between source register "cnt[4]" and destination register "cnt[11]" (period= 4.516 ns)
    Info: + Longest register to register delay is 4.275 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y12_N2; Fanout = 4; REG Node = 'cnt[4]'
        Info: 2: + IC(1.236 ns) + CELL(0.432 ns) = 1.668 ns; Loc. = LC_X21_Y11_N6; Fanout = 2; COMB Node = 'Add0~246COUT1'
        Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.748 ns; Loc. = LC_X21_Y11_N7; Fanout = 2; COMB Node = 'Add0~248COUT1'
        Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.828 ns; Loc. = LC_X21_Y11_N8; Fanout = 2; COMB Node = 'Add0~250COUT1'
        Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 2.086 ns; Loc. = LC_X21_Y11_N9; Fanout = 6; COMB Node = 'Add0~252'
        Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.765 ns; Loc. = LC_X21_Y10_N3; Fanout = 1; COMB Node = 'Add0~259'
        Info: 7: + IC(1.201 ns) + CELL(0.309 ns) = 4.275 ns; Loc. = LC_X20_Y13_N2; Fanout = 4; REG Node = 'cnt[11]'
        Info: Total cell delay = 1.838 ns ( 42.99 % )
        Info: Total interconnect delay = 2.437 ns ( 57.01 % )
    Info: - Smallest clock skew is 0.020 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X20_Y13_N2; Fanout = 4; REG Node = 'cnt[11]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clk" to source register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X21_Y12_N2; Fanout = 4; REG Node = 'cnt[4]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "data_reg[2]" (data pin = "wr_en", clock pin = "clk") is 5.894 ns
    Info: + Longest pin to register delay is 8.799 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_158; Fanout = 10; PIN Node = 'wr_en'
        Info: 2: + IC(6.463 ns) + CELL(0.867 ns) = 8.799 ns; Loc. = LC_X22_Y12_N7; Fanout = 1; REG Node = 'data_reg[2]'
        Info: Total cell delay = 2.336 ns ( 26.55 % )
        Info: Total interconnect delay = 6.463 ns ( 73.45 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.942 ns
        Info: 1: + IC(0.000 ns) + CEL