pulse.vhd

fredivn.vhd 偶数分频 fredivn1.vhd 奇数分频 frediv16.vhd 16分频 PULSE.vhd 数控分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PULSE IS
    PORT (   CLK  : IN STD_LOGIC;
               D  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             FOUT : OUT STD_LOGIC  );
END PULSE;
ARCHITECTURE beh OF PULSE IS
    SIGNAL   FULL : STD_LOGIC;
BEGIN
  P_REG: PROCESS(CLK)
   VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
   BEGIN           
      IF CLK'EVENT AND CLK = '1' THEN
            IF CNT8 = "11111111" THEN   
              CNT8 := D;       --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8    
              FULL <= '1';                  --同时使溢出标志信号FULL输出为高电平               
                ELSE   CNT8 := CNT8 + 1;  --否则继续作加1计数
                         FULL <= '0';       --且输出溢出标志信号FULL为低电平       
            END IF;
	  END IF;
    END PROCESS P_REG ;
   P_DIV: PROCESS(FULL)
     VARIABLE CNT2 : STD_LOGIC;
   BEGIN
   IF FULL'EVENT AND FULL = '1' 
       THEN  CNT2 := NOT CNT2;    --如果溢出标志信号FULL为高电平，D触发器输出取反
         IF CNT2 = '1' THEN  
FOUT <= '1'; 
           ELSE      
FOUT <= '0';
        END IF;
   END IF;
    END PROCESS P_DIV ;
END beh;