shuzi.map.rpt

可预置数字钟

; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                    ;
+------------------------+-------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Wed Nov 28 12:39:07 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SHUZI -c SHUZI
Info: Found 2 design units, including 1 entities, in source file F_M.vhd
    Info: Found design unit 1: F_M-behav
    Info: Found entity 1: F_M
Info: Found 2 design units, including 1 entities, in source file JW.vhd
    Info: Found design unit 1: JW-behav
    Info: Found entity 1: JW
Info: Found 2 design units, including 1 entities, in source file SHI.vhd
    Info: Found design unit 1: SHI-behav
    Info: Found entity 1: SHI
Info: Found 2 design units, including 1 entities, in source file SHIZHI.vhd
    Info: Found design unit 1: SHIZHI-behav
    Info: Found entity 1: SHIZHI
Info: Found 2 design units, including 1 entities, in source file SHUZI.vhd
    Info: Found design unit 1: SHUZI-fd1
    Info: Found entity 1: SHUZI
Info: Found 2 design units, including 1 entities, in source file SM.vhd
    Info: Found design unit 1: SM-behav
    Info: Found entity 1: SM
Info: Found 2 design units, including 1 entities, in source file ZT.vhd
    Info: Found design unit 1: ZT-behav
    Info: Found entity 1: ZT
Info: Elaborating entity "SHUZI" for the top level hierarchy
Info: Elaborating entity "ZT" for hierarchy "ZT:u1"
Info: Elaborating entity "JW" for hierarchy "JW:u2"
Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable "JW1", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable "JW2", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable "JW3", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "JW3" at JW.vhd(11)
Info (10041): Inferred latch for "JW2" at JW.vhd(11)
Info (10041): Inferred latch for "JW1" at JW.vhd(11)
Info: Elaborating entity "SHIZHI" for hierarchy "SHIZHI:u3"
Info: Elaborating entity "F_M" for hierarchy "F_M:u4"
Info: Elaborating entity "SHI" for hierarchy "SHI:u6"
Info: Elaborating entity "SM" for hierarchy "SM:u7"
Warning (10492): VHDL Process Statement warning at SM.vhd(20): signal "BT" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SM.vhd(21): signal "MIAO" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SM.vhd(22): signal "MIAO" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SM.vhd(23): signal "FEN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SM.vhd(24): signal "FEN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SM.vhd(25): signal "DIAN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at SM.vhd(26): signal "DIAN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at SM.vhd(13): inferring latch(es) for signal or variable "Y", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at SM.vhd(13): inferring latch(es) for signal or variable "CQ", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "CQ[0]" at SM.vhd(13)
Info (10041): Inferred latch for "CQ[1]" at SM.vhd(13)
Info (10041): Inferred latch for "CQ[2]" at SM.vhd(13)
Info (10041): Inferred latch for "CQ[3]" at SM.vhd(13)
Info (10041): Inferred latch for "Y[0]" at SM.vhd(13)
Info (10041): Inferred latch for "Y[1]" at SM.vhd(13)
Info (10041): Inferred latch for "Y[2]" at SM.vhd(13)
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add0"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add0|addcore:adder", which is child of megafunction instantiation "F_M:u4|lpm_add_sub:Add0"
Info: Instantiated megafunction "F_M:u4|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:oflow_node", which is child of megafunction instantiation "F_M:u4|lpm_add_sub:Add0"
Info: Instantiated megafunction "F_M:u4|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node", which is child of megafunction instantiation "F_M:u4|lpm_add_sub:Add0"
Info: Instantiated megafunction "F_M:u4|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "F_M:u4|lpm_add_sub:Add0"
Info: Instantiated megafunction "F_M:u4|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "F_M:u4|lpm_add_sub:Add0"
Info: Instantiated megafunction "F_M:u4|lpm_add_sub:Add0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "8"
    Info: Parameter "LPM_DIRECTION" = "ADD"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info: Elaborated megafunction instantiation "F_M:u4|lpm_add_sub:Add1"
Warning: Latch SM:u7|Y[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal SM:u7|BT[1]
Warning: Latch SM:u7|Y[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal SM:u7|BT[2]
Warning: Latch SM:u7|CQ[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal SM:u7|BT[2]
Warning: Latch SM:u7|CQ[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal SM:u7|BT[2]
Warning: Latch SM:u7|CQ[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal SM:u7|BT[2]
Warning: Latch SM:u7|CQ[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal SM:u7|BT[2]
Warning: Latch JW:u2|JW2 has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ZT:u1|Z[2]
Warning: Latch JW:u2|JW1 has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ZT:u1|Z[2]
Warning: Latch JW:u2|JW3 has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal ZT:u1|Z[2]
Info: Implemented 146 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 8 output pins
    Info: Implemented 133 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
    Info: Allocated 149 megabytes of memory during processing
    Info: Processing ended: Wed Nov 28 12:39:11 2007
    Info: Elapsed time: 00:00:04