shuzi.map.qmsg

可预置数字钟

{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "BT SM.vhd(20) " "Warning (10492): VHDL Process Statement warning at SM.vhd(20): signal \"BT\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MIAO SM.vhd(21) " "Warning (10492): VHDL Process Statement warning at SM.vhd(21): signal \"MIAO\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MIAO SM.vhd(22) " "Warning (10492): VHDL Process Statement warning at SM.vhd(22): signal \"MIAO\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 22 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "FEN SM.vhd(23) " "Warning (10492): VHDL Process Statement warning at SM.vhd(23): signal \"FEN\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 23 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "FEN SM.vhd(24) " "Warning (10492): VHDL Process Statement warning at SM.vhd(24): signal \"FEN\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 24 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DIAN SM.vhd(25) " "Warning (10492): VHDL Process Statement warning at SM.vhd(25): signal \"DIAN\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DIAN SM.vhd(26) " "Warning (10492): VHDL Process Statement warning at SM.vhd(26): signal \"DIAN\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "Y SM.vhd(13) " "Warning (10631): VHDL Process Statement warning at SM.vhd(13): inferring latch(es) for signal or variable \"Y\", which holds its previous value in one or more paths through the process" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "CQ SM.vhd(13) " "Warning (10631): VHDL Process Statement warning at SM.vhd(13): inferring latch(es) for signal or variable \"CQ\", which holds its previous value in one or more paths through the process" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "CQ\[0\] SM.vhd(13) " "Info (10041): Inferred latch for \"CQ\[0\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "CQ\[1\] SM.vhd(13) " "Info (10041): Inferred latch for \"CQ\[1\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "CQ\[2\] SM.vhd(13) " "Info (10041): Inferred latch for \"CQ\[2\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "CQ\[3\] SM.vhd(13) " "Info (10041): Inferred latch for \"CQ\[3\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Y\[0\] SM.vhd(13) " "Info (10041): Inferred latch for \"Y\[0\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Y\[1\] SM.vhd(13) " "Info (10041): Inferred latch for \"Y\[1\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "Y\[2\] SM.vhd(13) " "Info (10041): Inferred latch for \"Y\[2\]\" at SM.vhd(13)" {  } { { "SM.vhd" "" { Text "E:/SHUZIZHONG/SM.vhd" 13 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf" 102 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "F_M:u4\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"F_M:u4\|lpm_add_sub:Add0\"" {  } { { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "F_M:u4\|lpm_add_sub:Add0\|addcore:adder F_M:u4\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"F_M:u4\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"F_M:u4\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.tdf" 268 4 0 } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "F_M:u4\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"F_M:u4\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 8 " "Info: Parameter \"LPM_WIDTH\" = \"8\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "F_M:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node F_M:u4\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"F_M:u4\|lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"F_M:u4\|lpm_add_sub:Add0\"" {  } { { "addcore.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/71/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}