shuzi.hier_info

可预置数字钟

|SHUZI
DIAO => SHIZHI:u3.DIAO
DIAO => JW:u2.DIAO
GONG => ZT:u1.GONG
RST => SHI:u6.RST
RST => F_M:u5.RST
RST => F_M:u4.RST
RST => SHIZHI:u3.RST
RST => ZT:u1.RST
CLK1 => JW:u2.CLK1
CLK2 => SM:u7.CLK2
C0 <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
Y[0] <= SM:u7.Y[0]
Y[1] <= SM:u7.Y[1]
Y[2] <= SM:u7.Y[2]
CQ[0] <= SM:u7.CQ[0]
CQ[1] <= SM:u7.CQ[1]
CQ[2] <= SM:u7.CQ[2]
CQ[3] <= SM:u7.CQ[3]


|SHUZI|ZT:u1
GONG => Z[2].CLK
GONG => Z[1].CLK
GONG => Z[0].CLK
RST => Z[2].ACLR
RST => Z[1].ACLR
RST => Z[0].ACLR
ZHUANG[0] <= Z[0].DB_MAX_OUTPUT_PORT_TYPE
ZHUANG[1] <= Z[1].DB_MAX_OUTPUT_PORT_TYPE
ZHUANG[2] <= Z[2].DB_MAX_OUTPUT_PORT_TYPE


|SHUZI|JW:u2
DIAO => Mux2.IN6
DIAO => Mux1.IN6
DIAO => Mux0.IN6
CLK1 => Mux2.IN7
CO1 => Mux1.IN7
CO2 => Mux0.IN7
ZHUANG[0] => Mux3.IN10
ZHUANG[0] => Mux2.IN10
ZHUANG[0] => Mux1.IN10
ZHUANG[0] => Mux0.IN10
ZHUANG[1] => Mux3.IN9
ZHUANG[1] => Mux2.IN9
ZHUANG[1] => Mux1.IN9
ZHUANG[1] => Mux0.IN9
ZHUANG[2] => Mux3.IN8
ZHUANG[2] => Mux2.IN8
ZHUANG[2] => Mux1.IN8
ZHUANG[2] => Mux0.IN8
JW1 <= JW1$latch.DB_MAX_OUTPUT_PORT_TYPE
JW2 <= JW2$latch.DB_MAX_OUTPUT_PORT_TYPE
JW3 <= JW3$latch.DB_MAX_OUTPUT_PORT_TYPE


|SHUZI|SHIZHI:u3
RST => SZI.ACLR
DIAO => SZI.CLK
ZHUANG[0] => Equal0.IN5
ZHUANG[1] => Equal0.IN4
ZHUANG[2] => Equal0.IN3
SZ[0] <= <VCC>
SZ[1] <= SZI.DB_MAX_OUTPUT_PORT_TYPE
SZ[2] <= <GND>
SZ[3] <= <GND>
SZ[4] <= SZI.DB_MAX_OUTPUT_PORT_TYPE
SZ[5] <= SZI.DB_MAX_OUTPUT_PORT_TYPE
SZ[6] <= <GND>
SZ[7] <= <GND>


|SHUZI|F_M:u4
RST => CQI[7].ACLR
RST => CQI[6].ACLR
RST => CQI[5].ACLR
RST => CQI[4].ACLR
RST => CQI[3].ACLR
RST => CQI[2].ACLR
RST => CQI[1].ACLR
RST => CQI[0].ACLR
RST => CO~reg0.ENA
JW => CQI[7].CLK
JW => CQI[6].CLK
JW => CQI[5].CLK
JW => CQI[4].CLK
JW => CQI[3].CLK
JW => CQI[2].CLK
JW => CQI[1].CLK
JW => CQI[0].CLK
JW => CO~reg0.CLK
FM[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
FM[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
FM[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
FM[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
FM[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE
FM[5] <= CQI[5].DB_MAX_OUTPUT_PORT_TYPE
FM[6] <= CQI[6].DB_MAX_OUTPUT_PORT_TYPE
FM[7] <= CQI[7].DB_MAX_OUTPUT_PORT_TYPE
CO <= CO~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SHUZI|F_M:u5
RST => CQI[7].ACLR
RST => CQI[6].ACLR
RST => CQI[5].ACLR
RST => CQI[4].ACLR
RST => CQI[3].ACLR
RST => CQI[2].ACLR
RST => CQI[1].ACLR
RST => CQI[0].ACLR
RST => CO~reg0.ENA
JW => CQI[7].CLK
JW => CQI[6].CLK
JW => CQI[5].CLK
JW => CQI[4].CLK
JW => CQI[3].CLK
JW => CQI[2].CLK
JW => CQI[1].CLK
JW => CQI[0].CLK
JW => CO~reg0.CLK
FM[0] <= CQI[0].DB_MAX_OUTPUT_PORT_TYPE
FM[1] <= CQI[1].DB_MAX_OUTPUT_PORT_TYPE
FM[2] <= CQI[2].DB_MAX_OUTPUT_PORT_TYPE
FM[3] <= CQI[3].DB_MAX_OUTPUT_PORT_TYPE
FM[4] <= CQI[4].DB_MAX_OUTPUT_PORT_TYPE
FM[5] <= CQI[5].DB_MAX_OUTPUT_PORT_TYPE
FM[6] <= CQI[6].DB_MAX_OUTPUT_PORT_TYPE
FM[7] <= CQI[7].DB_MAX_OUTPUT_PORT_TYPE
CO <= CO~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SHUZI|SHI:u6
JW => \P1:CQI[7].CLK
JW => \P1:CQI[6].CLK
JW => \P1:CQI[5].CLK
JW => \P1:CQI[4].CLK
JW => \P1:CQI[3].CLK
JW => \P1:CQI[2].CLK
JW => \P1:CQI[1].CLK
JW => \P1:CQI[0].CLK
RST => \P1:CQI[7].ACLR
RST => \P1:CQI[6].ACLR
RST => \P1:CQI[5].ACLR
RST => \P1:CQI[4].ACLR
RST => \P1:CQI[3].ACLR
RST => \P1:CQI[2].ACLR
RST => \P1:CQI[1].ACLR
RST => \P1:CQI[0].ACLR
SZ[0] => LessThan1.IN8
SZ[1] => LessThan1.IN7
SZ[2] => LessThan1.IN6
SZ[3] => LessThan1.IN5
SZ[4] => LessThan1.IN4
SZ[5] => LessThan1.IN3
SZ[6] => LessThan1.IN2
SZ[7] => LessThan1.IN1
XS[0] <= \P1:CQI[0].DB_MAX_OUTPUT_PORT_TYPE
XS[1] <= \P1:CQI[1].DB_MAX_OUTPUT_PORT_TYPE
XS[2] <= \P1:CQI[2].DB_MAX_OUTPUT_PORT_TYPE
XS[3] <= \P1:CQI[3].DB_MAX_OUTPUT_PORT_TYPE
XS[4] <= \P1:CQI[4].DB_MAX_OUTPUT_PORT_TYPE
XS[5] <= \P1:CQI[5].DB_MAX_OUTPUT_PORT_TYPE
XS[6] <= \P1:CQI[6].DB_MAX_OUTPUT_PORT_TYPE
XS[7] <= \P1:CQI[7].DB_MAX_OUTPUT_PORT_TYPE


|SHUZI|SM:u7
CLK2 => BT[2].CLK
CLK2 => BT[1].CLK
CLK2 => BT[0].CLK
MIAO[0] => Mux0.IN3
MIAO[1] => Mux1.IN3
MIAO[2] => Mux2.IN3
MIAO[3] => Mux3.IN3
MIAO[4] => Mux0.IN2
MIAO[5] => Mux1.IN2
MIAO[6] => Mux2.IN2
MIAO[7] => Mux3.IN2
FEN[0] => Mux0.IN5
FEN[1] => Mux1.IN5
FEN[2] => Mux2.IN5
FEN[3] => Mux3.IN5
FEN[4] => Mux0.IN4
FEN[5] => Mux1.IN4
FEN[6] => Mux2.IN4
FEN[7] => Mux3.IN4
DIAN[0] => Mux0.IN7
DIAN[1] => Mux1.IN7
DIAN[2] => Mux2.IN7
DIAN[3] => Mux3.IN7
DIAN[4] => Mux0.IN6
DIAN[5] => Mux1.IN6
DIAN[6] => Mux2.IN6
DIAN[7] => Mux3.IN6
Y[0] <= Y[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Y[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Y[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
CQ[0] <= CQ[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
CQ[1] <= CQ[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
CQ[2] <= CQ[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
CQ[3] <= CQ[3]$latch.DB_MAX_OUTPUT_PORT_TYPE