sm.tan.qmsg

可预置数字钟

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "Y\[0\]\$latch " "Warning: Node \"Y\[0\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "Y\[1\]\$latch " "Warning: Node \"Y\[1\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "Y\[2\]\$latch " "Warning: Node \"Y\[2\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CQ\[0\]\$latch " "Warning: Node \"CQ\[0\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CQ\[1\]\$latch " "Warning: Node \"CQ\[1\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CQ\[2\]\$latch " "Warning: Node \"CQ\[2\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "CQ\[3\]\$latch " "Warning: Node \"CQ\[3\]\$latch\" is a latch" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 13 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK2 " "Info: Assuming node \"CLK2\" is an undefined clock" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 5 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux5~11 " "Info: Detected gated clock \"Mux5~11\" as buffer" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 20 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux5~11" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "BT\[1\] " "Info: Detected ripple clock \"BT\[1\]\" as buffer" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "BT\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "BT\[2\] " "Info: Detected ripple clock \"BT\[2\]\" as buffer" {  } { { "SM.vhd" "" { Text "E:/SM/SM.vhd" 15 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "BT\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}