jw.tan.rpt

可预置数字钟

+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+-----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From      ; To  ; From Clock ;
+-------+--------------+------------+-----------+-----+------------+
; N/A   ; None         ; 17.200 ns  ; JW1$latch ; JW1 ; ZHUANG[1]  ;
; N/A   ; None         ; 17.100 ns  ; JW1$latch ; JW1 ; ZHUANG[0]  ;
; N/A   ; None         ; 16.800 ns  ; JW1$latch ; JW1 ; ZHUANG[2]  ;
; N/A   ; None         ; 15.600 ns  ; JW3$latch ; JW3 ; ZHUANG[1]  ;
; N/A   ; None         ; 15.600 ns  ; JW2$latch ; JW2 ; ZHUANG[1]  ;
; N/A   ; None         ; 15.500 ns  ; JW3$latch ; JW3 ; ZHUANG[0]  ;
; N/A   ; None         ; 15.500 ns  ; JW2$latch ; JW2 ; ZHUANG[0]  ;
; N/A   ; None         ; 15.200 ns  ; JW3$latch ; JW3 ; ZHUANG[2]  ;
; N/A   ; None         ; 15.200 ns  ; JW2$latch ; JW2 ; ZHUANG[2]  ;
+-------+--------------+------------+-----------+-----+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+-----------+-----------+-----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To        ; To Clock  ;
+---------------+-------------+-----------+-----------+-----------+-----------+
; N/A           ; None        ; 2.000 ns  ; ZHUANG[2] ; JW1$latch ; ZHUANG[1] ;
; N/A           ; None        ; 1.900 ns  ; ZHUANG[2] ; JW1$latch ; ZHUANG[0] ;
; N/A           ; None        ; 1.600 ns  ; ZHUANG[2] ; JW1$latch ; ZHUANG[2] ;
; N/A           ; None        ; 0.100 ns  ; ZHUANG[2] ; JW2$latch ; ZHUANG[1] ;
; N/A           ; None        ; 0.000 ns  ; ZHUANG[1] ; JW3$latch ; ZHUANG[1] ;
; N/A           ; None        ; 0.000 ns  ; ZHUANG[2] ; JW2$latch ; ZHUANG[0] ;
; N/A           ; None        ; -0.100 ns ; ZHUANG[1] ; JW3$latch ; ZHUANG[0] ;
; N/A           ; None        ; -0.100 ns ; ZHUANG[2] ; JW3$latch ; ZHUANG[1] ;
; N/A           ; None        ; -0.200 ns ; ZHUANG[0] ; JW2$latch ; ZHUANG[1] ;
; N/A           ; None        ; -0.200 ns ; ZHUANG[2] ; JW3$latch ; ZHUANG[0] ;
; N/A           ; None        ; -0.300 ns ; ZHUANG[0] ; JW2$latch ; ZHUANG[0] ;
; N/A           ; None        ; -0.300 ns ; ZHUANG[2] ; JW2$latch ; ZHUANG[2] ;
; N/A           ; None        ; -0.400 ns ; ZHUANG[1] ; JW3$latch ; ZHUANG[2] ;
; N/A           ; None        ; -0.500 ns ; ZHUANG[2] ; JW3$latch ; ZHUANG[2] ;
; N/A           ; None        ; -0.600 ns ; ZHUANG[0] ; JW2$latch ; ZHUANG[2] ;
; N/A           ; None        ; -0.900 ns ; CLK1      ; JW1$latch ; ZHUANG[1] ;
; N/A           ; None        ; -1.000 ns ; CLK1      ; JW1$latch ; ZHUANG[0] ;
; N/A           ; None        ; -1.100 ns ; ZHUANG[0] ; JW1$latch ; ZHUANG[1] ;
; N/A           ; None        ; -1.200 ns ; ZHUANG[1] ; JW1$latch ; ZHUANG[1] ;
; N/A           ; None        ; -1.200 ns ; ZHUANG[0] ; JW1$latch ; ZHUANG[0] ;
; N/A           ; None        ; -1.300 ns ; ZHUANG[1] ; JW1$latch ; ZHUANG[0] ;
; N/A           ; None        ; -1.300 ns ; CLK1      ; JW1$latch ; ZHUANG[2] ;
; N/A           ; None        ; -1.400 ns ; DIAO      ; JW1$latch ; ZHUANG[1] ;
; N/A           ; None        ; -1.500 ns ; ZHUANG[0] ; JW1$latch ; ZHUANG[2] ;
; N/A           ; None        ; -1.500 ns ; DIAO      ; JW1$latch ; ZHUANG[0] ;
; N/A           ; None        ; -1.600 ns ; ZHUANG[1] ; JW1$latch ; ZHUANG[2] ;
; N/A           ; None        ; -1.800 ns ; DIAO      ; JW1$latch ; ZHUANG[2] ;
; N/A           ; None        ; -2.200 ns ; ZHUANG[1] ; JW2$latch ; ZHUANG[1] ;
; N/A           ; None        ; -2.200 ns ; ZHUANG[0] ; JW3$latch ; ZHUANG[1] ;
; N/A           ; None        ; -2.300 ns ; ZHUANG[1] ; JW2$latch ; ZHUANG[0] ;
; N/A           ; None        ; -2.300 ns ; ZHUANG[0] ; JW3$latch ; ZHUANG[0] ;
; N/A           ; None        ; -2.300 ns ; CO1       ; JW2$latch ; ZHUANG[1] ;
; N/A           ; None        ; -2.400 ns ; CO1       ; JW2$latch ; ZHUANG[0] ;
; N/A           ; None        ; -2.500 ns ; DIAO      ; JW2$latch ; ZHUANG[1] ;
; N/A           ; None        ; -2.500 ns ; DIAO      ; JW3$latch ; ZHUANG[1] ;
; N/A           ; None        ; -2.600 ns ; ZHUANG[1] ; JW2$latch ; ZHUANG[2] ;
; N/A           ; None        ; -2.600 ns ; ZHUANG[0] ; JW3$latch ; ZHUANG[2] ;
; N/A           ; None        ; -2.600 ns ; DIAO      ; JW2$latch ; ZHUANG[0] ;
; N/A           ; None        ; -2.600 ns ; DIAO      ; JW3$latch ; ZHUANG[0] ;
; N/A           ; None        ; -2.700 ns ; CO1       ; JW2$latch ; ZHUANG[2] ;
; N/A           ; None        ; -2.900 ns ; DIAO      ; JW2$latch ; ZHUANG[2] ;
; N/A           ; None        ; -2.900 ns ; DIAO      ; JW3$latch ; ZHUANG[2] ;
; N/A           ; None        ; -6.300 ns ; CO2       ; JW3$latch ; ZHUANG[1] ;
; N/A           ; None        ; -6.400 ns ; CO2       ; JW3$latch ; ZHUANG[0] ;
; N/A           ; None        ; -6.700 ns ; CO2       ; JW3$latch ; ZHUANG[2] ;
+---------------+-------------+-----------+-----------+-----------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Tue Nov 27 14:39:34 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off JW -c JW
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "JW1$latch" is a latch
    Warning: Node "JW2$latch" is a latch
    Warning: Node "JW3$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "ZHUANG[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "ZHUANG[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
    Info: Assuming node "ZHUANG[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux3~12" as buffer
Info: tsu for register "JW3$latch" (data pin = "CO2", clock pin = "ZHUANG[2]") is 10.500 ns
    Info: + Longest pin to register delay is 12.400 ns
        Info: 1: + IC(0.000 ns) + CELL(3.400 ns) = 3.400 ns; Loc. = PIN_15; Fanout = 1; PIN Node = 'CO2'
        Info: 2: + IC(2.700 ns) + CELL(1.900 ns) = 8.000 ns; Loc. = LC5_C23; Fanout = 1; COMB Node = 'Mux0~72'
        Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 10.200 ns; Loc. = LC6_C23; Fanout = 1; COMB Node = 'Mux0~73'
        Info: 4: + IC(0.200 ns) + CELL(2.000 ns) = 12.400 ns; Loc. = LC8_C23; Fanout = 1; REG Node = 'JW3$latch'
        Info: Total cell delay = 9.300 ns ( 75.00 % )
        Info: Total interconnect delay = 3.100 ns ( 25.00 % )
    Info: + Micro setup delay of destination is 3.800 ns
    Info: - Shortest clock path from clock "ZHUANG[2]" to destination register is 5.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; CLK Node = 'ZHUANG[2]'
        Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 3.800 ns; Loc. = LC1_C23; Fanout = 3; COMB Node = 'Mux3~12'
        Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.700 ns; Loc. = LC8_C23; Fanout = 1; REG Node = 'JW3$latch'
        Info: Total cell delay = 3.900 ns ( 68.42 % )
        Info: Total interconnect delay = 1.800 ns ( 31.58 % )
Info: tco from clock "ZHUANG[1]" to destination pin "JW1" through register "JW1$latch" is 17.200 ns
    Info: + Longest clock path from clock "ZHUANG[1]" to source register is 7.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 4; CLK Node = 'ZHUANG[1]'
        Info: 2: + IC(1.700 ns) + CELL(2.000 ns) = 4.200 ns; Loc. = LC1_C23; Fanout = 3; COMB Node = 'Mux3~12'
        Info: 3: + IC(2.000 ns) + CELL(1.700 ns) = 7.900 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1$latch'
        Info: Total cell delay = 4.200 ns ( 53.16 % )
        Info: Total interconnect delay = 3.700 ns ( 46.84 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 9.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1$latch'
        Info: 2: + IC(0.700 ns) + CELL(8.600 ns) = 9.300 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'JW1'
        Info: Total cell delay = 8.600 ns ( 92.47 % )
        Info: Total interconnect delay = 0.700 ns ( 7.53 % )
Info: th for register "JW1$latch" (data pin = "ZHUANG[2]", clock pin = "ZHUANG[1]") is 2.000 ns
    Info: + Longest clock path from clock "ZHUANG[1]" to destination register is 7.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 4; CLK Node = 'ZHUANG[1]'
        Info: 2: + IC(1.700 ns) + CELL(2.000 ns) = 4.200 ns; Loc. = LC1_C23; Fanout = 3; COMB Node = 'Mux3~12'
        Info: 3: + IC(2.000 ns) + CELL(1.700 ns) = 7.900 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1$latch'
        Info: Total cell delay = 4.200 ns ( 53.16 % )
        Info: Total interconnect delay = 3.700 ns ( 46.84 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 5.900 ns
        Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_78; Fanout = 4; CLK Node = 'ZHUANG[2]'
        Info: 2: + IC(1.500 ns) + CELL(1.700 ns) = 3.700 ns; Loc. = LC1_C7; Fanout = 1; COMB Node = 'Mux2~67'
        Info: 3: + IC(0.200 ns) + CELL(2.000 ns) = 5.900 ns; Loc. = LC5_C7; Fanout = 1; REG Node = 'JW1$latch'
        Info: Total cell delay = 4.200 ns ( 71.19 % )
        Info: Total interconnect delay = 1.700 ns ( 28.81 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 6 warnings
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Tue Nov 27 14:39:36 2007
    Info: Elapsed time: 00:00:02