jw.vhd

来自「可预置数字钟」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JW IS
PORT(DIAO,CLK1,CO1,CO2:IN STD_LOGIC;
                ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
           JW1,JW2,JW3:OUT STD_LOGIC );
END JW;
ARCHITECTURE behav OF JW IS
BEGIN
PROCESS(ZHUANG,CLK1,CO1,CO2,DIAO)
BEGIN
 CASE ZHUANG IS
     WHEN "000" => JW1<=CLK1;JW2<=CO1;JW3<=CO2;
     WHEN "001" => JW1<='0';JW2<='0';JW3<=DIAO;
     WHEN "010" => JW1<='0';JW2<=DIAO;JW3<='0';
     WHEN "011" => JW1<=DIAO;JW2<='0';JW3<='0';
     WHEN "100" => JW1<='0';JW2<='0';JW3<='0';
     WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END behav;