prev_cmp_jw.qmsg

可预置数字钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 27 14:38:52 2007 " "Info: Processing started: Tue Nov 27 14:38:52 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off JW -c JW " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off JW -c JW" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "JW.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file JW.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 JW-behav " "Info: Found design unit 1: JW-behav" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 JW " "Info: Found entity 1: JW" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "JW " "Info: Elaborating entity \"JW\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "JW1 JW.vhd(11) " "Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable \"JW1\", which holds its previous value in one or more paths through the process" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "JW2 JW.vhd(11) " "Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable \"JW2\", which holds its previous value in one or more paths through the process" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "JW3 JW.vhd(11) " "Warning (10631): VHDL Process Statement warning at JW.vhd(11): inferring latch(es) for signal or variable \"JW3\", which holds its previous value in one or more paths through the process" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "JW3 JW.vhd(11) " "Info (10041): Inferred latch for \"JW3\" at JW.vhd(11)" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "JW2 JW.vhd(11) " "Info (10041): Inferred latch for \"JW2\" at JW.vhd(11)" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "JW1 JW.vhd(11) " "Info (10041): Inferred latch for \"JW1\" at JW.vhd(11)" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "JW1\$latch " "Warning: Latch JW1\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA ZHUANG\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal ZHUANG\[2\]" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "JW2\$latch " "Warning: Latch JW2\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA ZHUANG\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal ZHUANG\[2\]" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "JW3\$latch " "Warning: Latch JW3\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA ZHUANG\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal ZHUANG\[2\]" {  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 6 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "JW.vhd" "" { Text "E:/JW/JW.vhd" 11 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "20 " "Info: Implemented 20 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "10 " "Info: Implemented 10 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 27 14:38:55 2007 " "Info: Processing ended: Tue Nov 27 14:38:55 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}