prev_cmp_shizhi.map.qmsg

可预置数字钟

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 27 19:54:17 2007 " "Info: Processing started: Tue Nov 27 19:54:17 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SHIZHI -c SHIZHI " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SHIZHI -c SHIZHI" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "SHIZHI.vhd 2 1 " "Warning: Using design file SHIZHI.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SHIZHI-behav " "Info: Found design unit 1: SHIZHI-behav" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 SHIZHI " "Info: Found entity 1: SHIZHI" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SHIZHI " "Info: Elaborating entity \"SHIZHI\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RST SHIZHI.vhd(14) " "Warning (10492): VHDL Process Statement warning at SHIZHI.vhd(14): signal \"RST\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 14 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SZ\[0\] VCC " "Warning: Pin \"SZ\[0\]\" stuck at VCC" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SZ\[2\] GND " "Warning: Pin \"SZ\[2\]\" stuck at GND" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SZ\[3\] GND " "Warning: Pin \"SZ\[3\]\" stuck at GND" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SZ\[6\] GND " "Warning: Pin \"SZ\[6\]\" stuck at GND" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SZ\[7\] GND " "Warning: Pin \"SZ\[7\]\" stuck at GND" {  } { { "SHIZHI.vhd" "" { Text "E:/SHIZHI/SHIZHI.vhd" 7 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "15 " "Info: Implemented 15 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 27 19:54:19 2007 " "Info: Processing ended: Tue Nov 27 19:54:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}