cntnbit.vhd

来自「俩个比较好的计数器的vhdl代码：一个是n位通用计数器」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cntnbit is
	generic(n : positive :=4);
	port(clock, reset, enable : in std_logic;
		count : out std_logic_vector((n-1) downto 0));
end cntnbit;

architecture v1 of cntnbit is
	signal count_int : std_logic_vector((n-1) downto 0);
begin
	process
	begin
		wait until rising_edge(clock);
		if reset = '1' then
			count_int <= (others => '0');
		elsif enable = '1' then
			count_int <= count_int + 1;
		else
			null;
		end if;
	end process;
count <= count_int;
end v1;