prev_cmp_ocmj2x8.tan.qmsg

用verilog写的对OCMJ2X8液晶模块控制代码

{ "Info" "ITDB_TH_RESULT" "lcd_db\[4\]~reg0 nrst clkin 6.800 ns register " "Info: th for register \"lcd_db\[4\]~reg0\" (data pin = \"nrst\", clock pin = \"clkin\") is 6.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 10.800 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_cnt\[1\] 2 REG LC1_C1 25 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C1; Fanout = 25; REG Node = 'clk_cnt\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clkin clk_cnt[1] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.800 ns lcd_db\[4\]~reg0 3 REG LC6_A6 2 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.800 ns; Loc. = LC6_A6; Fanout = 2; REG Node = 'lcd_db\[4\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { clk_cnt[1] lcd_db[4]~reg0 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.11 % ) " "Info: Total cell delay = 3.900 ns ( 36.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 63.89 % ) " "Info: Total interconnect delay = 6.900 ns ( 63.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] lcd_db[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} lcd_db[4]~reg0 {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns nrst 1 PIN PIN_2 34 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_2; Fanout = 34; PIN Node = 'nrst'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nrst } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.200 ns) 5.600 ns lcd_db\[4\]~reg0 2 REG LC6_A6 2 " "Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 5.600 ns; Loc. = LC6_A6; Fanout = 2; REG Node = 'lcd_db\[4\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { nrst lcd_db[4]~reg0 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 71.43 % ) " "Info: Total cell delay = 4.000 ns ( 71.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 28.57 % ) " "Info: Total interconnect delay = 1.600 ns ( 28.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { nrst lcd_db[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { nrst {} nrst~out {} lcd_db[4]~reg0 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] lcd_db[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} lcd_db[4]~reg0 {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { nrst lcd_db[4]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { nrst {} nrst~out {} lcd_db[4]~reg0 {} } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.800ns 1.200ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 20 19:12:41 2008 " "Info: Processing ended: Sun Apr 20 19:12:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}