prev_cmp_ocmj2x8.tan.qmsg

用verilog写的对OCMJ2X8液晶模块控制代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_cnt\[1\] " "Info: Detected ripple clock \"clk_cnt\[1\]\" as buffer" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 9 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_cnt\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register fsm_cnt\[3\] register fsm_cnt\[0\] 47.62 MHz 21.0 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 47.62 MHz between source register \"fsm_cnt\[3\]\" and destination register \"fsm_cnt\[0\]\" (period= 21.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.400 ns + Longest register register " "Info: + Longest register to register delay is 17.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fsm_cnt\[3\] 1 REG LC2_A15 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A15; Fanout = 15; REG Node = 'fsm_cnt\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { fsm_cnt[3] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.700 ns) 4.600 ns Equal0~100 2 COMB LC2_A17 2 " "Info: 2: + IC(2.900 ns) + CELL(1.700 ns) = 4.600 ns; Loc. = LC2_A17; Fanout = 2; COMB Node = 'Equal0~100'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.600 ns" { fsm_cnt[3] Equal0~100 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 6.100 ns Equal0~95 3 COMB LC3_A17 4 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 6.100 ns; Loc. = LC3_A17; Fanout = 4; COMB Node = 'Equal0~95'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { Equal0~100 Equal0~95 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 10.600 ns fsm_cnt~939 4 COMB LC8_A18 1 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 10.600 ns; Loc. = LC8_A18; Fanout = 1; COMB Node = 'fsm_cnt~939'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Equal0~95 fsm_cnt~939 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 13.500 ns fsm_cnt~940 5 COMB LC1_A18 1 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 13.500 ns; Loc. = LC1_A18; Fanout = 1; COMB Node = 'fsm_cnt~940'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { fsm_cnt~939 fsm_cnt~940 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 17.400 ns fsm_cnt\[0\] 6 REG LC1_A13 15 " "Info: 6: + IC(2.200 ns) + CELL(1.700 ns) = 17.400 ns; Loc. = LC1_A13; Fanout = 15; REG Node = 'fsm_cnt\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { fsm_cnt~940 fsm_cnt[0] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.500 ns ( 54.60 % ) " "Info: Total cell delay = 9.500 ns ( 54.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 45.40 % ) " "Info: Total interconnect delay = 7.900 ns ( 45.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.400 ns" { fsm_cnt[3] Equal0~100 Equal0~95 fsm_cnt~939 fsm_cnt~940 fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.400 ns" { fsm_cnt[3] {} Equal0~100 {} Equal0~95 {} fsm_cnt~939 {} fsm_cnt~940 {} fsm_cnt[0] {} } { 0.000ns 2.900ns 0.000ns 2.200ns 0.600ns 2.200ns } { 0.000ns 1.700ns 1.500ns 2.300ns 2.300ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 10.800 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_cnt\[1\] 2 REG LC1_C1 25 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C1; Fanout = 25; REG Node = 'clk_cnt\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clkin clk_cnt[1] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.800 ns fsm_cnt\[0\] 3 REG LC1_A13 15 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.800 ns; Loc. = LC1_A13; Fanout = 15; REG Node = 'fsm_cnt\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.11 % ) " "Info: Total cell delay = 3.900 ns ( 36.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 63.89 % ) " "Info: Total interconnect delay = 6.900 ns ( 63.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 10.800 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_cnt\[1\] 2 REG LC1_C1 25 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C1; Fanout = 25; REG Node = 'clk_cnt\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clkin clk_cnt[1] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.800 ns fsm_cnt\[3\] 3 REG LC2_A15 15 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.800 ns; Loc. = LC2_A15; Fanout = 15; REG Node = 'fsm_cnt\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { clk_cnt[1] fsm_cnt[3] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.11 % ) " "Info: Total cell delay = 3.900 ns ( 36.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 63.89 % ) " "Info: Total interconnect delay = 6.900 ns ( 63.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[3] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[3] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.400 ns" { fsm_cnt[3] Equal0~100 Equal0~95 fsm_cnt~939 fsm_cnt~940 fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.400 ns" { fsm_cnt[3] {} Equal0~100 {} Equal0~95 {} fsm_cnt~939 {} fsm_cnt~940 {} fsm_cnt[0] {} } { 0.000ns 2.900ns 0.000ns 2.200ns 0.600ns 2.200ns } { 0.000ns 1.700ns 1.500ns 2.300ns 2.300ns 1.700ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[3] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "fsm_cnt\[0\] lcd_busy clkin 9.200 ns register " "Info: tsu for register \"fsm_cnt\[0\]\" (data pin = \"lcd_busy\", clock pin = \"clkin\") is 9.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.500 ns + Longest pin register " "Info: + Longest pin to register delay is 17.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns lcd_busy 1 PIN PIN_44 21 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_44; Fanout = 21; PIN Node = 'lcd_busy'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd_busy } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.300 ns) 7.200 ns Selector14~93 2 COMB LC4_A21 1 " "Info: 2: + IC(2.100 ns) + CELL(2.300 ns) = 7.200 ns; Loc. = LC4_A21; Fanout = 1; COMB Node = 'Selector14~93'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { lcd_busy Selector14~93 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 9.600 ns Selector14~94 3 COMB LC7_A21 1 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 9.600 ns; Loc. = LC7_A21; Fanout = 1; COMB Node = 'Selector14~94'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { Selector14~93 Selector14~94 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.800 ns) 13.600 ns fsm_cnt~940 4 COMB LC1_A18 1 " "Info: 4: + IC(2.200 ns) + CELL(1.800 ns) = 13.600 ns; Loc. = LC1_A18; Fanout = 1; COMB Node = 'fsm_cnt~940'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { Selector14~94 fsm_cnt~940 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 17.500 ns fsm_cnt\[0\] 5 REG LC1_A13 15 " "Info: 5: + IC(2.200 ns) + CELL(1.700 ns) = 17.500 ns; Loc. = LC1_A13; Fanout = 15; REG Node = 'fsm_cnt\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { fsm_cnt~940 fsm_cnt[0] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.400 ns ( 59.43 % ) " "Info: Total cell delay = 10.400 ns ( 59.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns ( 40.57 % ) " "Info: Total interconnect delay = 7.100 ns ( 40.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.500 ns" { lcd_busy Selector14~93 Selector14~94 fsm_cnt~940 fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.500 ns" { lcd_busy {} lcd_busy~out {} Selector14~93 {} Selector14~94 {} fsm_cnt~940 {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.100ns 0.600ns 2.200ns 2.200ns } { 0.000ns 2.800ns 2.300ns 1.800ns 1.800ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 10.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_cnt\[1\] 2 REG LC1_C1 25 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C1; Fanout = 25; REG Node = 'clk_cnt\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clkin clk_cnt[1] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.800 ns fsm_cnt\[0\] 3 REG LC1_A13 15 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.800 ns; Loc. = LC1_A13; Fanout = 15; REG Node = 'fsm_cnt\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.11 % ) " "Info: Total cell delay = 3.900 ns ( 36.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 63.89 % ) " "Info: Total interconnect delay = 6.900 ns ( 63.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.500 ns" { lcd_busy Selector14~93 Selector14~94 fsm_cnt~940 fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.500 ns" { lcd_busy {} lcd_busy~out {} Selector14~93 {} Selector14~94 {} fsm_cnt~940 {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.100ns 0.600ns 2.200ns 2.200ns } { 0.000ns 2.800ns 2.300ns 1.800ns 1.800ns 1.700ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] fsm_cnt[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} fsm_cnt[0] {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin lcd_db\[0\] lcd_db\[0\]~reg0 22.900 ns register " "Info: tco from clock \"clkin\" to destination pin \"lcd_db\[0\]\" through register \"lcd_db\[0\]~reg0\" is 22.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 10.800 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 10.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clkin 1 CLK PIN_43 2 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 2; CLK Node = 'clkin'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk_cnt\[1\] 2 REG LC1_C1 25 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_C1; Fanout = 25; REG Node = 'clk_cnt\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { clkin clk_cnt[1] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.800 ns lcd_db\[0\]~reg0 3 REG LC1_A23 2 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.800 ns; Loc. = LC1_A23; Fanout = 2; REG Node = 'lcd_db\[0\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { clk_cnt[1] lcd_db[0]~reg0 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns ( 36.11 % ) " "Info: Total cell delay = 3.900 ns ( 36.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 63.89 % ) " "Info: Total interconnect delay = 6.900 ns ( 63.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] lcd_db[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} lcd_db[0]~reg0 {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.000 ns + Longest register pin " "Info: + Longest register to pin delay is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd_db\[0\]~reg0 1 REG LC1_A23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A23; Fanout = 2; REG Node = 'lcd_db\[0\]~reg0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lcd_db[0]~reg0 } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.900 ns) + CELL(5.100 ns) 11.000 ns lcd_db\[0\] 2 PIN PIN_71 0 " "Info: 2: + IC(5.900 ns) + CELL(5.100 ns) = 11.000 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'lcd_db\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { lcd_db[0]~reg0 lcd_db[0] } "NODE_NAME" } } { "OCMJ2X8.v" "" { Text "E:/Mywork/EDA/Altera/FPGA/EPF10K_Lab/OCMJ2X8/OCMJ2X8.v" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 46.36 % ) " "Info: Total cell delay = 5.100 ns ( 46.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.900 ns ( 53.64 % ) " "Info: Total interconnect delay = 5.900 ns ( 53.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { lcd_db[0]~reg0 lcd_db[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { lcd_db[0]~reg0 {} lcd_db[0] {} } { 0.000ns 5.900ns } { 0.000ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.800 ns" { clkin clk_cnt[1] lcd_db[0]~reg0 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.800 ns" { clkin {} clkin~out {} clk_cnt[1] {} lcd_db[0]~reg0 {} } { 0.000ns 0.000ns 2.500ns 4.400ns } { 0.000ns 2.800ns 1.100ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.000 ns" { lcd_db[0]~reg0 lcd_db[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.000 ns" { lcd_db[0]~reg0 {} lcd_db[0] {} } { 0.000ns 5.900ns } { 0.000ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}