ocmj2x8.v

用verilog写的对OCMJ2X8液晶模块控制代码

module OCMJ2X8(clkin,nrst,lcd_req,lcd_busy,lcd_db);
input clkin,nrst,lcd_busy;
output lcd_req;
output[7:0] lcd_db;
reg lcd_req;
reg[7:0] lcd_db;

parameter clk_div_wth = 2;			//**************
reg[clk_div_wth-1:0] clk_cnt;
wire clk1;

reg[3:0] mstate;
reg[7:0] fsm_cnt;
parameter idle		= 4'b0000;
parameter clear_a	= 4'b0001;
parameter clear_b	= 4'b0010;
parameter clear_c	= 4'b0011;
parameter wrdata_a	= 4'b0100;
parameter wrdata_b	= 4'b0101;
parameter wrdata_c	= 4'b0110;
parameter delay		= 4'b1111;

function[7:0] ddram;
	input[5:0] n;
	begin
		case(n)
			6'b00_0000:ddram=8'b1111_0000;     	//xian shi han zi
			6'b00_0001:ddram=8'b0000_0000;		//X
			6'b00_0010:ddram=8'b0000_0000;		//Y
			6'b00_0011:ddram=8'd41;
			6'b00_0100:ddram=8'd47;		//上

			6'b00_0101:ddram=8'b1111_0000;     	//xian shi han zi
			6'b00_0110:ddram=8'b0000_0001;		//X
			6'b00_0111:ddram=8'b0000_0000;		//Y
			6'b00_1000:ddram=8'd26;
			6'b00_1001:ddram=8'd03;		//海

			6'b00_1010:ddram=8'b1111_0000;     	//xian shi han zi
			6'b00_1011:ddram=8'b0000_0010;		//X
			6'b00_1100:ddram=8'b0000_0000;		//Y
			6'b00_1101:ddram=8'd20;
			6'b00_1110:ddram=8'd83;		//大

			6'b00_1111:ddram=8'b1111_0000;     	//xian shi han zi
			6'b01_0000:ddram=8'b0000_0011;		//X
			6'b01_0001:ddram=8'b0000_0000;		//Y
			6'b01_0010:ddram=8'd49;
			6'b01_0011:ddram=8'd07;		//学

			6'b01_0100:ddram=8'b1111_0000;     	//xian shi han zi
			6'b01_0101:ddram=8'b0000_0100;		//X
			6'b01_0110:ddram=8'b0000_0000;		//Y
			6'b01_0111:ddram=8'd46;
			6'b01_1000:ddram=8'd02;		//微

			6'b01_1001:ddram=8'b1111_0000;     	//xian shi han zi
			6'b01_1010:ddram=8'b0000_0101;		//X
			6'b01_1011:ddram=8'b0000_0000;		//Y
			6'b01_1100:ddram=8'd21;
			6'b01_1101:ddram=8'd71;		//电

			6'b01_1110:ddram=8'b1111_0000;     	//xian shi han zi
			6'b01_1111:ddram=8'b0000_0110;		//X
			6'b10_0000:ddram=8'b0000_0000;		//Y
			6'b10_0001:ddram=8'd55;
			6'b10_0010:ddram=8'd51;		//子

			default:ddram=8'b1111_0100;			//clear
		endcase
	end
endfunction	
	
function[7:0] ASCII8X8;
	input[5:0] n;
	begin
		case(n)
			6'b00_0000:ASCII8X8=8'hf1;     	
			6'b00_0001:ASCII8X8=8'h00;		
			6'b00_0010:ASCII8X8=8'h00;		
			6'b00_0011:ASCII8X8=8'h30;	//0
	
			6'b00_0100:ASCII8X8=8'hf1;		
			6'b00_0101:ASCII8X8=8'h01;     	
			6'b00_0110:ASCII8X8=8'h00;		
			6'b00_0111:ASCII8X8=8'h31;	//1
	
			6'b00_1000:ASCII8X8=8'hf1;
			6'b00_1001:ASCII8X8=8'h02;		
			6'b00_1010:ASCII8X8=8'h00;     	
			6'b00_1011:ASCII8X8=8'h32;	//2	
	
			6'b00_1100:ASCII8X8=8'hf1;		
			6'b00_1101:ASCII8X8=8'h03;
			6'b00_1110:ASCII8X8=8'h00;		
			6'b00_1111:ASCII8X8=8'h33;  	//3   	
	
			6'b01_0000:ASCII8X8=8'hf1;		
			6'b01_0001:ASCII8X8=8'h04;		
			6'b01_0010:ASCII8X8=8'h00;
			6'b01_0011:ASCII8X8=8'h34;	//4	
			
			6'b01_0100:ASCII8X8=8'hf1;     	
			6'b01_0101:ASCII8X8=8'h05;		
			6'b01_0110:ASCII8X8=8'h00;		
			6'b01_0111:ASCII8X8=8'h35;	//5
	
			6'b01_1000:ASCII8X8=8'hf1;		
			6'b01_1001:ASCII8X8=8'h06;     	
			6'b01_1010:ASCII8X8=8'h00;		
			6'b01_1011:ASCII8X8=8'h36;	//6
	
			6'b01_1100:ASCII8X8=8'hf1;
			6'b01_1101:ASCII8X8=8'h07;		
			6'b01_1110:ASCII8X8=8'h00;     	
			6'b01_1111:ASCII8X8=8'h37;	//7		
	
			6'b10_0000:ASCII8X8=8'hf1;		
			6'b10_0001:ASCII8X8=8'h08;
			6'b10_0010:ASCII8X8=8'h00;		
			6'b10_0011:ASCII8X8=8'h38;  	//8   	
	
			6'b10_0100:ASCII8X8=8'hf1;		
			6'b10_0101:ASCII8X8=8'h09;		
			6'b10_0110:ASCII8X8=8'h00;
			6'b10_0111:ASCII8X8=8'h39;	//9	
	
			default:ASCII8X8=8'b1111_0100;			
		endcase
	end
endfunction
 
always@(posedge clkin)
	clk_cnt <= clk_cnt + 1;
	
assign clk1 = clk_cnt[clk_div_wth-1];

always@(posedge clk1)
	begin
		if(!nrst)
			begin
				mstate <= idle;
				fsm_cnt <= 8'b0000_0001;				//***************
			end
		else
			begin
				case(mstate)
					idle:
						begin
							lcd_req <= 0;
							if(!fsm_cnt)
								mstate <=clear_a;
							else
								begin
									fsm_cnt <= fsm_cnt - 1;
									mstate <= idle;
								end
						end
					clear_a:
						begin
							if(!lcd_busy)
								begin
									lcd_db <=8'hf4;
									mstate <= clear_b;
								end
							else
								mstate <=clear_a;
						end
					clear_b:
						begin
							lcd_req <= 1;
							mstate <=clear_c;
						end
					clear_c:
						begin
							if(lcd_busy)
								begin
									lcd_req <= 0;
									mstate <= wrdata_a;
									fsm_cnt <= 0;
								end
							else
								mstate <= clear_c;
						end
					wrdata_a:
						begin
							if(!lcd_busy)
								begin
									//lcd_db <=ddram(fsm_cnt);	//显示汉字用这句，禁止下面一句
									lcd_db <=ASCII8X8(fsm_cnt);	//显示数字用这句，禁止上面一句
									mstate <= wrdata_b;
								end
							else
								mstate <=wrdata_a;
						end
					wrdata_b:
						begin
							lcd_req <= 1;
							mstate <=wrdata_c;
							fsm_cnt <= fsm_cnt+1;
						end
					wrdata_c:
						begin
							if(lcd_busy)
								begin
									lcd_req <= 0;
									//if(fsm_cnt==35)		//显示汉字用这句，禁止下面一句
									if(fsm_cnt==40) 		//显示数字用这句，禁止上面一句
										mstate <= delay;
									else
										mstate <= wrdata_a;
								end
							else
								mstate <= wrdata_c;
						end
					delay:
						begin
							if(!lcd_busy)
								mstate <= delay;//idle;
							else
								mstate <= delay;
						end
					default:mstate <= idle;
				endcase			
			end
	end
	
endmodule