repeat_1s.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 28 行

//-------------------------------
//Count one bits in a 8-bit word
//using repeat loop
//Filename : repeat_1s.v
//-------------------------------
module repeat_1s(ones, Din);

output [3:0] ones;	  //Output the number of ones
parameter length = 8; //data length
input [length-1:0] Din; //8-bit data input

reg [length-1:0] tmpr;
reg [3:0] ones;
reg [3:0] Cout;
always @ (Din)
 begin
  Cout = 4'b0000;
  tmpr = Din;	

  repeat (length)
   begin
    if (tmpr[0]) Cout = Cout + 4'b0001;
    tmpr = tmpr >> 1;    //shift right 
   end
   ones = Cout;
 end
 
endmodule