repeat_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();

reg [7:0] Din;	 // Inputs

wire [3:0] ones;// Outputs

repeat_1s uut (.ones(ones), .Din(Din));// Instantiate the UUT

// Initialize Inputs
initial
 $monitor ($time, "ones =%d,  Din =%b", ones, Din);

initial	//Initialize input signals
   Din =8'b00000000;

initial 
  begin
   #10  Din = 8'b01010101; //Set different values for Din
   #10  Din = 8'b11001101;
   #10  Din = 8'b00000100;
   #10  Din = 8'b11110101;
   #10  Din = 8'b01100111;
   #10  Din = 8'b10000010;
   #10  Din = 8'b00111100;
   #10  Din = 8'b10110101;
  end

initial #100 $finish;        //Complete simulation after 100 units
endmodule