gra2bin_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg [7:0] Gry;

// Outputs
    wire [7:0] Bin;

// Instantiate the UUT
    gra2bin uut (.Gry(Gry), .Bin(Bin));

reg [7:0] i;

// Initialize Inputs
initial
 $monitor ($time, "  Gry=%b,Bin=%b", Gry, Bin);

initial	//Initialize input signals
   Gry =8'b00000000;

initial 
 for (i=0; i<256; i=i+1)
   #10  Gry = Gry+1;

initial #2560 $finish;        //Complete simulation after 2560 units

endmodule