gra2bin.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//--------------------------------------
//Convert 8-bit Gray code to binary code 
//using for loop
//filename : gra2bin.v
//--------------------------------------
module gra2bin(Gry, Bin);
parameter length = 8;       //8-bit length
output [length-1:0] Bin;    //Binary putput
input [length-1:0] Gry;     //Gray code input

reg [length-1:0] Bin;
integer i;

always @ (Gry)
 begin
  Bin[length-1]=Gry[length-1]; 
  for (i=length-2; i>=0; i = i-1)
 	 Bin[i]=Bin[i+1] ^ Gry[i];
 end
 
endmodule