demul1_4_if.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//---------------------------------------------------------
//1 to 4 Demultiplexer using nesting if...else..statement
//Filename: demul1_4_if.v
//---------------------------------------------------------
module demul1_4_if(y, I, S0, S1);
output [3:0] y;
input I;
input S0, S1;	    //Selection signals

reg [3:0] y;
always @ (I or S0 or S1)
  begin
    if (S1==1'b0)
     begin
	  if (S0==1'b0)
         y = {3'b000, I};	   //marge 000 with I to y
       else
         y = {2'b00, I, 1'b0};
	end
    else
     begin 
	  if (S0==1'b0)
         y = {1'b0, I, 2'b00};
       else
         y = {I, 3'b000};
	end
  end
endmodule