counter_simtb.tf

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· TF 代码 · 共 56 行

module testbench();

// DATE:     Mon Apr 28 15:26:36 2003 
// TITLE:    
// MODULE:   counter_sim
// DESIGN:   counter_sim
// FILENAME: counter_sim
// PROJECT:  counter_sim
// VERSION:  Version


// Inputs
    reg CLK;
    reg RESET;


// Outputs
    wire [7:0] COUNT;


// Bidirs
initial
    $monitor($time, "    COUNT = %d     RESET = %b", COUNT[7:0], RESET);

// Instantiate the UUT
    counter_sim uut (
        .CLK(CLK), 
        .RESET(RESET), 
        .COUNT(COUNT)
        );


// Stimulate the RESET signal
initial begin
   RESET = 1'b1;
   #45 RESET = 1'b0;
   #200 RESET = 1'b1;
   #50 RESET = 1'b0;
end

// Set up the clock to toggle every 100 time units
initial begin
     CLK = 1'b0;
	forever #10 CLK=~CLK;
end

//Finish the simulation at time 400
initial begin
     #400 $finish;
end

endmodule