encod8_3_casex.v
来自「FPGA开发板上写的Verilog代码: 功能是从电脑端发送一个字节」· Verilog 代码 · 共 23 行
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23 行
//------------------------------------
//8 to 3 encoder using casex statement
//Filename : encod8_3_casex.v
//------------------------------------
module encod8_3_casex(y,i);
output [2:0] y;
input [7:0] i;
reg [2:0] y;
always @ (i)
casex (i)
8'b???????1: y = 3'd000;
8'b??????10: y = 3'd001;
8'b?????100: y = 3'd010;
8'b????1000: y = 3'd011;
8'b???10000: y = 3'd100;
8'b??100000: y = 3'd101;
8'b?1000000: y = 3'd110;
8'b10000000: y = 3'd111;
default : y=3'bzzz;
endcase
endmodule
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