reg4_bpa.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//--------------------------------------------------
//4-bit register for Blocking Procedural Assignment
//Filename : reg_bpa.v
//--------------------------------------------------
module reg4_bpa(Qout, CLK, RESET, Din);
output [3:0] Qout;
input CLK, RESET;
input Din;

reg [3:0] Qout;

 
always @ (posedge CLK or posedge RESET)
//Positive edge CLK and asynchronous RESET
 if (RESET)
   Qout = 4'b0000;
 else
  begin
   Qout[0] = Din;
   Qout[1] = Qout[0];
   Qout[2] = Qout[1];
   Qout[3] = Qout[2];
  end
endmodule