ram16x8sng_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg clk;
    reg we;
    reg [3:0] ADDR;
    reg [7:0] Din;


// Outputs
    wire [7:0] Dout;

// Instantiate the UUT
    RAM16x8sng uut (
        .clk(clk), 
        .we(we), 
        .ADDR(ADDR), 
        .Din(Din), 
        .Dout(Dout)
        );

// Initialize Inputs
initial
 $monitor ($time, "Dout=%h, Din=%b, ADDR=%d, we=%b, clk=%b", Dout, Din, ADDR, we, clk);

initial
 begin
   forever #10 clk=~clk;	//Set clock with a period 20 units
 end

initial	//Initialize input signals
 begin
  #0  clk=0; we=0;
  #10 Din=8'h00;ADDR=4'h0;we=1; //Write several data into RAM
  #20 we=0;
  #10 Din=8'h22;ADDR=4'h1;we=1;
  #20 we=0;  
  #10 Din=8'h44;ADDR=4'h2;we=1;
  #20 we=0;
  #10 Din=8'h66;ADDR=4'h3;we=1;
  #20 we=0;
  #10 Din=8'h88;ADDR=4'h4;we=1;
  #20 we=0;
  #10 Din=8'hAA;ADDR=4'h5;we=1;
  #20 we=0;
  #10 Din=8'hBB;ADDR=4'h6;we=1;
  #20 we=0;
  #10 Din=8'hCC;ADDR=4'h7;we=1;
  #20 we=0;
  #20 ADDR=4'h0;	      //Read data 
  #20 ADDR=4'h1;
  #20 ADDR=4'h2;
  #20 ADDR=4'h3;
  #20 ADDR=4'h4;
  #20 ADDR=4'h5;
  #20 ADDR=4'h6;
  #20 ADDR=4'h7;
 end

initial #500 $finish;        //Complete simulation after 500 units

endmodule