bin2gra.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 20 行

//--------------------------------------
//Convert 8-bit binary code to Gray code
//using for loop
//filename : bin2gra.v
//--------------------------------------
module bin2gra(Gry, Bin);
parameter length = 8;       //8-bit length
output [length-1:0] Gry;    //Gray code putput
input [length-1:0] Bin;     //Binary input

reg [length-1:0] Gry;
integer i;

always @ (Bin)
 begin 
  for (i=0; i<length-1; i = i+1)
 	 Gry[i]=Bin[i] ^ Bin[i+1];
  Gry[i] = Bin[i];
 end
endmodule