bin2gra_tb.tf

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· TF 代码 · 共 31 行

module testbench();

// Inputs
    reg [7:0] Bin;

// Outputs
    wire [7:0] Gry;

// Instantiate the UUT
    bin2gra uut (.Gry(Gry), .Bin(Bin));

reg [7:0] i;

// Initialize Inputs
initial
 $monitor ($time, "Bin=%b,  Gry=%b", Bin, Gry);

initial	//Initialize input signals
   Bin =8'b00000000;

initial 
 for (i=0; i<256; i=i+1)
   #10  Bin = Bin+1;

initial #2560 $finish;        //Complete simulation after 2560 units

endmodule