mul4_2_1.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//--------------------------------
//4-bt 2 to 1 multiplexer
//Filename: mul4_2_1.v
//--------------------------------
module mul4_2_1(y, s, a, b);
output [3:0] y;
input s;           //Select signal
input [3:0] a, b;  //Input data

reg [3:0] y;

always @ (s or a or b)
 if (s)
   y = b;
 else
   y = a;

endmodule