comp4_if.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//-----------------------------------------
// 4-bit Comparator with asynchronous reset
// (if...else if...else)
// Filename: comp4_if.v
//-----------------------------------------
module comp4_if(eq, gt, lt, a, b);

// Port Declarations
output eq, gt, lt;  //outputs eq:Equal, gt:Great than, lt:Less than
input [3:0] a, b; 	//4-bit inputs

reg eq, gt, lt;

always @ (a or b)
 begin
   if (a==b)
    begin
     eq = 1'b1; gt = 1'b0; lt = 1'b0;
    end
  else if (a > b)
    begin
     eq = 1'b0; gt = 1'b1; lt = 1'b0;
    end
  else
    begin
     eq = 1'b0; gt = 1'b0; lt = 1'b1;
    end
 end
endmodule