comp4_if_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();

// Inputs
    reg [3:0] a;
    reg [3:0] b;


// Outputs
    wire eq, gt, lt;


// Instantiate the UUT
    comp4_if comp4 (
        .eq(eq), 
        .gt(gt), 
        .lt(lt), 
        .a(a),
	   .b(b)
        );

initial
 $monitor ($time,"eq=%b, gt=%b, lt=%b, a=%b, b=%b", eq, gt, lt, a, b);

initial	//Initialize input signals
 begin
    a = 4'b0000;
    b = 4'b0000;
 end

initial 
 begin
   #20  a = 4'b1100;   //Set input data at different times
   #20  b = 4'b1010;
   #20  b = 4'b1101;
   #20  b = 4'b1100;
 end

initial #120 $finish;  //Complete simulation after 120 time units
  
endmodule