count_0s.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//-------------------------------
//Count zero bits in a 8-bit word
//using while loop
//Filename : count_0s.v
//-------------------------------
module count_0s(Cout, Din);
output [3:0] Cout;
input [7:0] Din;
reg [3:0] Cout;

reg [7:0] tmpr;
always @ (Din)
 begin
  Cout = 0;
  tmpr = Din;

  while (tmpr)
   begin
    if (~tmpr[0]) Cout = Cout + 4'b0001;
    tmpr = tmpr >> 1;    //shift right 
   end
 end

endmodule