shl4_for.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 25 行

//----------------------------------------
//4-bit shift left register using for loop
//filename : shl4_for.v
//----------------------------------------
module shl4_for(Q, CLK, RESET, Din);
parameter length = 4;
output [length-1:0] Q;
input CLK, RESET;
input Din;
integer i;
reg [3:0] Q;

always @ (posedge CLK)
 begin 
  if (RESET)
    Q = 4'b0000;
  else
   begin
    for (i=length-1; i>0; i = i-1)
      Q[i] = Q[i-1];
    Q[0] = Din;
   end
 end
endmodule