shl4_for_tb.tf

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· TF 代码 · 共 43 行

module testbench();
// Inputs
    reg CLK;
    reg RESET;
    reg Din;


// Outputs
    wire [3:0] Q;


// Instantiate the UUT
    shl4_for uut (.Q(Q), .CLK(CLK), .RESET(RESET), .Din(Din));


// Initialize Inputs

initial
 $monitor ($time, "Din=%b,  CLK=%b,  RESET=%b, Qout=%b", Din, CLK, RESET, Q);

initial	//Initialize input signals
 begin
    CLK = 0;
    RESET = 1;
    Din = 0;
 end

initial 
 begin
   #25  RESET = 0;	         //Disable RESET at time 25 units
   #10  Din = 1;             //Set Din at 10 units
   #100  RESET = 1;	         //Enable RESET at time 135 units
 end

always #10 CLK=~CLK;	    //Set clock with a period 20 units

initial #180 $finish;        //Complete simulation after 180 units
  
endmodule