latch4_if.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 18 行

//------------------------------------
//4-bit latch using if... statement
//Filename : latch4_if
//------------------------------------
module latch4_if(y, load, din);
output [3:0] y;
input load;     //latch signal
input [3:0] din;

reg [3:0] y;

always @ (y or load)
 begin
  if (load)
    y = din;
 end
endmodule