bcdadder4_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();
// Inputs
    reg Cin;
    reg [3:0] A;
    reg [3:0] B;


// Outputs
    wire [3:0] S;
    wire Cout;

// Instantiate the UUT
    BCDadder4 uut (
        .S(S), 
        .Cout(Cout),
        .Cin(Cin), 
        .A(A), 
        .B(B)
        );


// Initialize Inputs
initial
 $monitor ($time, "A=%h,  B=%h, Cin=%b,  S=%d, Cout=%d", A, B, Cin, S, Cout);

initial	//Initialize input signals
 begin
  #50 A=8;B=9;Cin=1;
  #50 A=2;B=3;Cin=0;
  #50 A=7;B=6;Cin=1;
  #50 A=3;B=1;Cin=0;
  #50 A=9;B=9;Cin=1;
 end


initial #600 $finish;        //Complete simulation after 400 units

endmodule