bcdadder4.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 43 行

//------------------------------------
//4-bit BCD adder
//Filename : BCDadder4.v
//------------------------------------
module BCDadder4(S, Cout, Cin, A, B);
output [3:0] S; //Sumation output
output Cout;    //Carry out
input Cin;      //Carry in
input [3:0] A, B;//Input data


wire [3:0] S_tmp;
wire C4;
reg [3:0] B_mod;
reg F;

//4-bit binary adder
adder4 BINADD(
            .S(S_tmp),
            .Cout(C4),
            .Cin(Cin),
            .A(A),
            .B(B)
           );

//Modify binary code with '0110'
adder4 MODADD(
            .S(S),
            .Cout(),
            .Cin(1'b0),
            .A(S_tmp),
            .B(B_mod)
           );

always @ (Cin or A or B or C4 or S_tmp)
 begin
  //F=C4+S3(S2+S1)
  F = (C4 | (S_tmp[3] & (S_tmp[2] | S_tmp[1])));
  B_mod = {1'b0, F, F, 1'b0}; //Modified code
 end
assign Cout = F;
endmodule