mul3_1_casez.v

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

//---------------------------------------
//4-bit 3 to 1 multiplexer with priority
//Filename: mul3_1_case.v
//---------------------------------------
module mul3_1_casez(y, sel, a, b, c);
output [3:0] y;
input [2:0] sel;
input [3:0] a, b, c;

reg [3:0] y;

always @ (sel or a or b or c)
 begin
  casez (sel)
   3'bzz1 : y=a;
   3'bz10 : y=b;
   3'b100 : y=c;
   default : y=4'bzzzz;
  endcase
 end
endmodule