adder8_for.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 28 行

//----------------------------------------
//8-bit adder using for loop
//Filename : adder8_for.v
//----------------------------------------
module adder8_for(sum, cout, a, b, cin);
parameter length = 8;               //Data length
output [length-1:0] sum;            //Summation
output cout;                        //Carry out
input [length-1:0] a, b;            //Data input
input cin;                          //Carry in
reg carry;                          //Internal Carry
integer i;                          //Loop parameter

reg [ length-1:0] sum;
reg cout;
always @ (a or b or cin or carry)
 begin
  carry = cin;
  i = 0;
  for (i = 0; i<length; i = i+1)
    begin
      sum[i] = a[i] ^ b[i] ^ carry;
	 carry = a[i] & b[i] | a[i] & carry | b[i] & carry;
    end
  cout = carry;
 end
endmodule