first_0_tb.tf

FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节

module testbench();

reg [7:0] data_seq;
integer i;

initial begin
   data_seq = 8'b11001111; //testing data
   i=0;
   begin: search_loop
    while(i<8)
     begin
      if (!data_seq[i])
	  begin
	   $display("The first 0 bit is at position bit %d", i);
	   disable search_loop;
	  end
      i=i+1;
     end
   end
 end
endmodule