first_0.v

来自「FPGA开发板上写的Verilog代码： 功能是从电脑端发送一个字节」· Verilog 代码 · 共 23 行

//----------------------------------
//Search the first 0 in a 8-bit word
//Filename : first_0.v
//----------------------------------
module first_0(Dout, RESET);
parameter length = 8;
output [length-1:0] Dout;
input RESET;

reg [length-1:0] Dout;
reg [length-1:0] count;

always
 begin : search1
     count=count+1;
 end

always @ (negedge RESET)
     disable search1;

 //position = pos_tmp;
endmodule