pwm.map.summary

实现PWM波型....使用VHDL语言

Flow Status : Successful - Mon May 14 22:16:41 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : pwm
Top-level Entity Name : pwm
Family : Stratix
Met timing requirements : N/A
Total logic elements : 30
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0